Single long-scroll page with anchor links. Replaces:
Specification, Schematic, Layout, Simulation, Altium, Failure-Analysis
(6 old pages merged into 1).
Top anchor nav: FMEDA · RISC-V / SoC · Verification
· Board & PCB · Due Diligence
1. Functional Safety &
FMEDA (ISO 26262)
Safety-critical silicon and board designs live or die on diagnostic
coverage. FMEDA — Failure Modes, Effects, and Diagnostic Analysis — is
where that coverage gets proven to auditors.
What I deliver: – FMEDA spreadsheets and reports for
ASIL-A through ASIL-D parts – Failure rate (FIT) budgets per subsystem –
Diagnostic coverage modeling, including latent-fault detection – Safety
mechanisms: lockstep cores, ECC strategies, watchdog architectures, BIST
– Safety case artifacts: assumptions of use, safety goals, safety
requirements traceability – Pre-audit gap analysis — what your existing
documentation is missing before the certification body arrives
Typical engagements: – Review an existing FMEDA and
identify gaps (1–2 weeks) – Build an FMEDA from scratch for a new IP or
module (3–8 weeks) – On-call safety engineer during an active
certification cycle
Tools & standards: ISO 26262, IEC 61508
(adjacent), IEC 62304 (medical), DO-254 (airborne) — core methodology
transfers across all four.
2. RISC-V / SoC Architecture
I’ve been defining silicon for over two decades — from custom cores
at IBM and Apple to full SoC architecture at APCON and Intensivate-era
RISC-V work.
What I deliver: – Core specifications: ISA profile
selection, pipeline definition, microarchitecture trade-offs – Cache and
memory hierarchy design (L1/L2/L3, coherence protocol choice, MMU/PMP
configuration) – Custom ISA extensions for domain-specific workloads –
Full SoC integration: bus fabric (AXI, CHI, TileLink), NoC topology,
power domains, clock domains – Architecture reviews — does the proposed
design actually meet the performance, power, and area targets, and if
not, where’s the leak? – Pre-RTL modeling (cycle-approximate SystemC or
pure-Python)
Typical engagements: – Design review (1 week, fixed
scope) – Architecture definition for a new core or SoC (1–3 months) –
Advisory retainer — monthly check-in + on-call for a team doing their
own implementation
3. Verification & Emulation
Verification eats schedules. I’ve spent years pushing testbenches,
formal, and emulation platforms to close coverage faster.
What I deliver: – Simulation-based
verification: SystemVerilog + UVM testbenches,
constrained-random generation, functional coverage closure –
Formal verification: JasperGold, Synopsys Formal.
Property specification, assume/assert strategy, bounded and unbounded
proofs – Specification-level verification: TLA+ models
for protocol correctness before RTL exists – Emulation
bring-up: Synopsys ZeBu and HAPS platforms. Design
partitioning, clock domain handling, DUT instrumentation, regression
flows – FPGA prototyping: Xilinx-based prototypes for
software bring-up ahead of tape-out – Tool ownership:
Synopsys VCS and Verdi, Cadence Xcelium, waveform-first debug
methodology
Typical engagements: – Testbench audit — find
coverage gaps in an existing environment (1–2 weeks) – Formal property
set for a new block (2–6 weeks) – ZeBu/HAPS bring-up for a new SoC (4–12
weeks) – TLA+ model for a contested protocol spec (1–3 weeks)
4. Board-Level Analog/Digital
& PCB
Most of my board work is mixed-signal: an FPGA or microcontroller
next to sensitive analog front-ends, clean power rails, and a fabric of
signal-integrity constraints.
What I deliver: – Schematic
capture: Altium, OrCAD, Allegro. Library management, BOM
discipline – Circuit analysis and design: analog
front-ends, power supplies (switchers and LDOs), clocking trees,
reset/brownout, level shifting, isolation – Simulation:
LTspice for analog, IBIS for signal integrity, thermal hand-analysis
with FEA if needed – PCB layout: multi-layer stackups
including buried capacitance, controlled impedance, blind/buried vias,
HDI. 4-layer to 20+ layers – Signal integrity and power
integrity: pre-layout constraint development, post-layout
extraction, 3D field solver analysis when warranted –
EMI/EMC: design for pre-compliance before you step into
the chamber – Fabrication: PCB manufacturing resource
available — I can take a design from schematic to populated board
without you chasing vendors
Typical engagements: – Circuit design only (customer
does layout) – Full schematic + PCB layout – Design review of an
existing board (1 week, fixed scope) – Failure analysis and debug on an
existing product
5. Technical Due Diligence
For VCs evaluating a hardware investment, acquirers inspecting a
target, or boards that want a second opinion on their own team’s
plans.
What I deliver: – Architecture
soundness: does the proposed silicon or system actually do what
the pitch claims? – Execution risk: are the schedules
realistic? Is the team sized for the work? What’s the critical path? –
IP review: freedom-to-operate check, open-source
license exposure, third-party IP dependencies – Team capability
assessment: interviews with key engineers, code/RTL samples,
tool proficiency – Comparable analysis: how does this
compare to what competitors are doing or have shipped? – Written
report: executive summary + detailed findings + risk-ranked
recommendations
Typical engagements: – Light DD — 1
week, documentation and interviews only – Standard DD —
2 weeks, includes one-day site visit and deeper code/RTL inspection –
Deep DD — 3–4 weeks, includes running hands-on
evaluation of the tech
All engagements by
negotiation
Scope, rate, and terms tailored to the project. Short reviews,
multi-month builds, fractional engineering — all on the table.