Serial, Networking & Storage

APB4 CAN 2.0B + CAN-FD Controller

Safety-instrumented CAN / CAN-FD bus node for ASIL-B automotive SoCs — every CAN variant from one RTL, validated and ready.

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ASIL-B

target

92.45%

SPFM

90.00%

LFM

PASS

FMEDA

45.5K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

APB4 CAN 2.0B + CAN-FD Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Safety-instrumented CAN / CAN-FD bus node for ASIL-B automotive SoCs — every CAN variant from one RTL, validated and ready. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

An APB4 CAN 2.0B + CAN-FD bus controller delivered as synthesizable SystemVerilog soft-IP, with a full on-chip serial engine — arbitration, bit stuffing, CRC, ACK, and error frames — and built-in ASIL B safety instrumentation.

Key Features

Full on-chip serial engine: 11-/29-bit IDs, bit stuffing, CRC-15/17/21, ACK, arbitration-loss detection, active error frames
Classic CAN, slow/fault-tolerant CAN and CAN-FD (up to 8 Mbit/s data, up to 64 B) — all runtime-selectable from one RTL
Single-ended can_tx/can_rx to any external ISO 11898-2/-3 transceiver; differential PHY, termination and ESD stay on the board
Hardware fault confinement: TEC/REC counters, error-warning → error-passive → bus-off, raised as err_code 3 (recovery not automatic)
Listen-only bus-monitoring mode for a non-intrusive diagnostic / bus-guardian node
ASIL-B diagnostics: config parity (err_code 1), RX SECDED (err_code 2), diverse-DMR FSM lockstep (err_code 9) into shared safety_monitor
APB4 slave with multi-slot TX mailbox, depth-configurable RX FIFO and ID/mask acceptance filter; SPFM 92.45%

Standards & Compliance

ISO 11898-1 (CAN 2.0B / CAN-FD), ISO 11898-2/-3 (external transceiver); ISO 26262 ASIL-B SEooC (incl. Part 9 dependent-failure analysis)

Functional Safety

ASIL-B (SEooC) · SPFM 92.45% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
can_fd #(
 .ADDR_W(6)
) u_can_fd (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in APB4 CAN 2.0B + CAN-FD Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space