RISC-V Cores & SoC Platform

RISC-V ACLINT Timer / Software-Interrupt Unit

RISC-V ACLINT (MSWI + SSWI + MTIMER) — the modern split CLINT successor for a two-hart subsystem, ASIL-B via layered DMR + parity.

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ASIL-B

target

100.00%

SPFM

100.00%

LFM

PASS

FMEDA

3.6K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

RISC-V ACLINT Timer / Software-Interrupt Unit routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

RISC-V ACLINT (MSWI + SSWI + MTIMER) — the modern split CLINT successor for a two-hart subsystem, ASIL-B via layered DMR + parity. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

1. Overview

RISC-V ACLINT (Advanced Core-Local Interruptor) — the modern CLINT v2 split into MTIMER (64-bit mtime + per-hart mtimecmp -> machine-timer interrupt mtip) and MSWI/SSWI (per-hart machine/supervisor software-interrupt pending bits msip/ssip), all behind one APB4 slave.

Key Features

MTIMER: 64-bit free-running mtime (gated by MTIME_CTRL.EN) plus a per-hart 64-bit mtimecmp; mtip[h] = (mtime >= mtimecmp[h]), resetting to all-ones so no spurious mtip fires before software programs a deadline
MSWI + SSWI: independent per-hart machine- and supervisor-level software-interrupt pending bits (msip[h]/ssip[h]) — the supervisor path has no equivalent in the legacy clint
Fixed two-hart APB4 decode (v0.1): one register aperture (p_paddr[6:2] selects MSIP/SSIP/MTIMECMP/MTIME/MTIME_CTRL); NHART is a parameter but the decode only reaches harts 0 and 1
ASIL-B complementary DMR on mtime and the control set (err_code 9) — a stuck counter or control bit breaks the q == ~q_cmpl invariant
ASIL-B per-32-bit-word even parity on every hart’s mtimecmp, both halves independently (err_code 1)
ASIL-B write-decode DMR + duplicated comparator (re-derived from the complementary mtime shadow) catch a mis-decoded/dropped compare write or a mis-evaluated deadline that parity cannot see (err_code 9), with a DFT-only FAULT_INJECT_CMP hook for the gate-level campaign
Catalog FMEDA: 3594 cells, SPFM 100.00%, LFM 100.00%, PMHF 0/h — PASS against the ASIL-B target with full margin

Standards & Compliance

RISC-V Privileged Architecture (ACLINT specification: MSWI/SSWI/MTIMER), AMBA APB4 (ARM IHI 0024); ISO 26262 ASIL-B SEooC (SPFM 100.00%, LFM 100.00%, PMHF 0/h)

Functional Safety

ASIL-B (SEooC) · SPFM 100.00% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	+	4*h MSIP[h] RW bit0 machine software interrupt pending
`0x08`	+	4*h SSIP[h] RW bit0 supervisor software interrupt pending
`0x10`	+	8*h MTIMECMP[h]_LO RW
`0x14`	+	8*h MTIMECMP[h]_HI RW
`0x20`	MTIME_LO	RW

…2 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
aclint #(
 .ADDR_W(6)
) u_aclint (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in RISC-V ACLINT Timer / Software-Interrupt Unit?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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