Bus Bridges & Interconnect

APB4 → TileLink-UL Bridge

The apbtotlul bridge presents an AMBA APB4 subordinate port and re-issues each accepted transfer as a single TileLink Uncached Lightweight (TL-UL)…

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ASIL-B

target

92.60%

SPFM

91.28%

LFM

PASS

FMEDA

1.2K

gates

1.1.0

version

The deliverable

What you’re licensing

The apbtotlul bridge presents an AMBA APB4 subordinate port and re-issues each accepted transfer as a single TileLink Uncached Lightweight (TL-UL)… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

The apb_to_tl_ul bridge presents an AMBA APB4 subordinate port and re-issues each accepted transfer as a single TileLink Uncached Lightweight (TL-UL) A-channel request on its manager port, letting any APB4 manager — a legacy MCU core, a test/debug controller, or an APB4 DMA channel — reach a TL-UL-addressed fabric or peripheral with no changes to either side.

Key Features

APB4 subordinate → TL-UL manager: one APB transfer becomes one TL-A request; single-outstanding, register-free (no address decode)
GET / PUT_FULL / PUT_PARTIAL mapping selected by PWRITE and PSTRB; APB address passed through verbatim
Single clock domain, no internal CDC; PREADY held low to back-pressure the manager for the full TL-UL round trip
2-of-3 TMR FSM: a single state-rail fault is MASKED — the bridge keeps running — and is flagged as err_code 9
Write/read SECDED datapath ECC: SBE corrected, DBE → err_code 2; config/address parity → err_code 1
Configurable transaction-timeout monitor (err_code 4); TL-D denied / timeout → APB PSLVERR
Two independent error surfaces — functional (PSLVERR) vs safety (err_valid / err_code). SPFM 92.60% ASIL-B PASS

Standards & Compliance

AMBA APB4 (ARM IHI 0024) / TileLink-UL (OpenTitan) — ISO 26262 ASIL-B SEooC

Functional Safety

ASIL-B (SEooC) · SPFM 92.60% · LFM 91.28% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
apb_to_tl_ul #(
  .ADDR_W(6)
) u_apb_to_tl_ul (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in heterogeneous SoCs that mix AMBA and TileLink IP and need clean, verified protocol and clock-domain crossings.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in APB4 → TileLink-UL Bridge?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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