Avionics, Space & Mil-Std Networking

ARINC 717 Flight-Data-Recorder Bus Controller

ARINC 717 Flight-Data-Recorder (FDR) bus controller with an APB4-lite slave and an ASIL-B safety monitor.

Request this IP →Browse the catalog

ASIL-B

target

91.30%

SPFM

88.03%

LFM

PASS

FMEDA

3.3K

gates

1.0.0

version

The deliverable

What you’re licensing

ARINC 717 Flight-Data-Recorder (FDR) bus controller with an APB4-lite slave and an ASIL-B safety monitor. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

ARINC 717 Flight-Data-Recorder (FDR) bus controller with an APB4-lite slave and an ASIL-B safety monitor.

Key Features

Hardware ARINC 717 superframe/subframe framing: SUPERFRAME = 4 SUBFRAMEs (4 s), each SUBFRAME = a unique 12-bit SYNC word (word 0) then (wps-1) 12-bit acquired-data words, at one of five word rates via CFG.WPS_SEL
Harvard bi-phase-L codec: every data bit is two half-cells (first = ~bit, second = bit); a cell with no mid-cell transition is a bi-phase violation -> err_code 3
Four independently reprogrammable 12-bit subframe sync words (SYNC12/SYNC34/SYNCSEL), reset default SF1=0x247/SF2=0x5B8/SF3=0xA47/SF4=0xDB8, shared by both the TX framer and RX decoder
16-deep TX and RX 12-bit word buffers decouple the APB4-lite register plane from real-time bit-serial wire timing; CTRL.TXBUF_LOAD_RST flushes the TX side
CTRL.LOOPBACK self-test folds the TX bi-phase stream into the RX decoder, exercising encode -> decode -> sync-acquire -> frame-lock end to end without an external FDAU or recorder
Complementary-DMR lockstep on the TX/RX framing FSMs and word/subframe counters (err_code 9), plus config-register even parity (err_code 1) and sync/subframe timeout detection — loss of frame sync (err_code 4), all latched by the shared safety_monitor
APB4-lite register map (4-byte stride): CTRL 0x00, STATUS 0x04, CFG 0x08, SYNC12 0x0C, SYNC34 0x10, SYNCSEL 0x14, TX_WORD 0x18, RX_WORD 0x1C, ERR 0x20 (W1C), IER 0x24, ISR 0x28 (W1C)

Standards & Compliance

ARINC 717 (Harvard bi-phase Flight-Data-Recorder bus, 768-12,288 bps); DO-254/ED-80 airborne electronic hardware design-assurance framing; ISO 26262 ASIL-B SEooC (SPFM 91.30%, LFM 88.03%, PMHF 5.41×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.30% · LFM 88.03% · PASS

ISO 26262-5 FMEDA method (transferable evidence for the RTCA DO-254 assurance case) · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]EN [1]LOOPBACK [2]TXBUF_LOAD_RST [3]reserved
`0x04`	STATUS	[0]TX_BUSY [1]RX_LOCKED [2]TX_SF_DONE [3]RX_SF_DONE [5:4]tx_subframe [7:6]rx_subframe [10:8]fsm_state [14:11]tx_word_…
`0x08`	CFG	[2:0]WPS_SEL (0=64 1=128 2=256 3=512 4=1024 wps) [3]CFG even-parity bit
`0x0C`	SYNC12	[11:0]SYNC1 — write SF1 sync; [27:16]=read-back; auto-targets SF index
`0x10`	SYNC34	[11:0]SYNC3 … (paired sync programming; see SYNCSEL)

…6 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
arinc717 #(
  .ADDR_W(6)
) u_arinc717 (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in avionics, defense, and space systems built to the ARINC, MIL-STD, and CCSDS standards.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in ARINC 717 Flight-Data-Recorder Bus Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · sales@circuit-design.space