CHI Interconnect & Coherency

AXI4-to-CHI Bridge

axitochi lets any AXI4 manager (CPU or DMA) issue into an AMBA 5 CHI coherent interconnect: it terminates a full AXI4 slave port and drives the CHI…

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ASIL-B

target

90.30%

SPFM

88.99%

LFM

PASS

FMEDA

5.0K

gates

0.1.0

version

The deliverable

What you’re licensing

axitochi lets any AXI4 manager (CPU or DMA) issue into an AMBA 5 CHI coherent interconnect: it terminates a full AXI4 slave port and drives the CHI… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

axi_to_chi lets any AXI4 manager (CPU or DMA) issue into an AMBA 5 CHI coherent interconnect: it terminates a full AXI4 slave port and drives the CHI Request Node (RN) request channels, translating each accepted AXI beat into a CHI ReadNoSnp/WriteNoSnpFull request and returning the Home Node’s completion on AXI B/R.

Key Features

Full AXI4 slave front-end: INCR bursts, one CHI request issued per AXI beat, address advancing by DATA_W/8 until the burst’s last beat
Non-coherent CHI requests: WriteNoSnpFull (write) / ReadNoSnp (read) — no snoop participation, so the bridge is never itself snooped
Single-outstanding command FSM, write-priority arbitration — trivially correct AXI ordering by construction (no reordering is possible)
Single clock domain, no internal CDC — one clk/rst_n pair verified against the RTL and tools/cdc_check/cdc.groups.axi_to_chi.json
Error mapping: a CHI RespErr sticky-latches AXI SLVERR on B/R over the remaining burst and raises err_code 3 on the safety interface
ASIL-B overlay: config + AXI-address parity (err_code 1), read-data-buffer inline SECDED (err_code 2), outstanding-transaction watchdog (err_code 4), command-FSM diverse-DMR lockstep (err_code 9)
Catalog FMEDA (pre-sign-off engineering numbers): SPFM 90.30%, LFM 88.99%, PMHF 9.71×10⁻⁹/h — PASS against the ASIL-B target

Standards & Compliance

AMBA AXI4 (slave, INCR bursts); AMBA 5 CHI (RN request: TXREQ/TXDAT/RXRSP/RXDAT); APB4 config; ISO 26262 ASIL-B SEooC (SPFM 90.30%, LFM 88.99%, PMHF 9.71×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 90.30% · LFM 88.99% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN (accept AXI transactions)
`0x0C`	STATUS	RO [7:0]=FSM state [11:8]=err_code [12]=err_valid

Getting Started

// Minimal instantiation
axi_to_chi #(
  .ADDR_W(6)
) u_axi_to_chi (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in multi-core compute clusters that need cache coherency with a defensible ordering proof.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in AXI4-to-CHI Bridge?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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