CHI Interconnect & Coherency

AXI4-to-CHI Retaining-Cache RN-F Bridge

axitochirc is the retaining-cache (v3) tier of the axitochi AXI4-to-CHI bridge family: an AXI4 slave front-end that behaves as a genuine CHI Request…

Request this IP →Browse the catalog

ASIL-B

target

91.98%

SPFM

90.30%

LFM

PASS

FMEDA

22.1K

gates

0.1.0

version

The deliverable

What you’re licensing

axitochirc is the retaining-cache (v3) tier of the axitochi AXI4-to-CHI bridge family: an AXI4 slave front-end that behaves as a genuine CHI Request… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

axi_to_chi_rc is the retaining-cache (v3) tier of the axi_to_chi AXI4-to-CHI bridge family: an AXI4 slave front-end that behaves as a genuine CHI Request Node with a cache (RN-F) rather than a pass-through bridge.

Key Features

Fully-associative N_LINES held-line cache (states I/UC/UD): read hit and write hit served/merged LOCALLY with zero CHI bus traffic; a read miss with the cache full of dirty lines serves through without retaining rather than issuing a WriteBack
CHI Direct Cache Transfer (DCT): a snoop of a dirty held line forwards the written data as SnpRespData (invalidate applied at snoop accept, race-free against a concurrent local write) — the cache-to-cache path a chi_hn_f v6+ Home Node consumes
Multi-outstanding reads: up to N_TXN CHI fetches in flight (TxnID = slot index), delivered on AXI R strictly in AR-acceptance order per ARID — a same-address AR is held off while a fetch to that line is already in flight
Read/write phase separation: AW accepted only with the read table empty, AR accepted only with the write FSM idle — no read/write hazard window
Single-beat AoU enforced in hardware: ARLEN/AWLEN must be 0 (one CHI line == one AXI transaction); a burst is flagged err_code 3 (protocol) instead of mis-sequenced
ASIL-B overlay: held-line + read-slot inline SECDED (err_code 2), config + per-entry cache tag/state parity (err_code 1), CHI RespErr/burst-AoU protocol fault (err_code 3), outstanding-transaction watchdog (err_code 4), and triple complementary diverse-DMR (write/read-slot-vector/snoop FSM, err_code 9)
Catalog FMEDA (pre-sign-off engineering numbers): SPFM 91.98%, LFM 90.30%, PMHF 3.75×10⁻⁸/h — PASS against the ASIL-B target, N=22149 synthesized cells

Standards & Compliance

AMBA 5 CHI (RN-F Request Node); AMBA AXI4; ISO 26262 ASIL-B SEooC (SPFM 91.98%, LFM 90.30%, PMHF 3.75×10⁻⁸/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.98% · LFM 90.30% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN (accept AXI transactions)
`0x0C`	STATUS	RO [6:0]=write-FSM state [11:8]=err_code [12]=err_valid

Getting Started

// Minimal instantiation
axi_to_chi_rc #(
  .ADDR_W(6)
) u_axi_to_chi_rc (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in multi-core compute clusters that need cache coherency with a defensible ordering proof.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in AXI4-to-CHI Retaining-Cache RN-F Bridge?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · sales@circuit-design.space