Block diagram
Physical implementation
What you’re licensing
AMBA-5 CHI Request Node with a real cache — AXI4 slave front-end, held-line retain + DCT dirty-forward, multi-outstanding, ASIL-B safety. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:
What it is
axi_to_chi_rc is the retaining-cache (v3) tier of the axi_to_chi AXI4-to-CHI bridge family: an AXI4 slave front-end that behaves as a genuine CHI Request Node with a cache (RN-F) rather than a pass-through bridge.
Key Features
- Fully-associative N_LINES held-line cache (states I/UC/UD): read hit and write hit served/merged LOCALLY with zero CHI bus traffic; a read miss with the cache full of dirty lines serves through without retaining rather than issuing a WriteBack
- CHI Direct Cache Transfer (DCT): a snoop of a dirty held line forwards the written data as SnpRespData (invalidate applied at snoop accept, race-free against a concurrent local write) — the cache-to-cache path a chi_hn_f v6+ Home Node consumes
- Multi-outstanding reads: up to N_TXN CHI fetches in flight (TxnID = slot index), delivered on AXI R strictly in AR-acceptance order per ARID — a same-address AR is held off while a fetch to that line is already in flight
- Read/write phase separation: AW accepted only with the read table empty, AR accepted only with the write FSM idle — no read/write hazard window
- Single-beat AoU enforced in hardware: ARLEN/AWLEN must be 0 (one CHI line == one AXI transaction); a burst is flagged err_code 3 (protocol) instead of mis-sequenced
- ASIL-B overlay: held-line + read-slot inline SECDED (err_code 2), config + per-entry cache tag/state parity (err_code 1), CHI RespErr/burst-AoU protocol fault (err_code 3), outstanding-transaction watchdog (err_code 4), and triple complementary diverse-DMR (write/read-slot-vector/snoop FSM, err_code 9)
- Catalog FMEDA (pre-sign-off engineering numbers): SPFM 91.98%, LFM 90.30%, PMHF 3.75×10⁻⁸/h — PASS against the ASIL-B target, N=22149 synthesized cells
Standards & Compliance
AMBA 5 CHI (RN-F Request Node); AMBA AXI4; ISO 26262 ASIL-B SEooC (SPFM 91.98%, LFM 90.30%, PMHF 3.75×10⁻⁸/h)
Functional Safety
ASIL-B (SEooC) · SPFM 91.98% · LFM 90.30% · PASS
ISO 26262:2018 · FMEDA available · Safety Manual included
Register Map
| Offset | Register | Description |
|---|---|---|
0x00 | CTRL | RW [0]=EN (accept AXI transactions) |
0x0C | STATUS | RO [6:0]=write-FSM state [11:8]=err_code [12]=err_valid |
Getting Started
// Minimal instantiation
axi_to_chi_rc #(
.ADDR_W(6)
) u_axi_to_chi_rc (
.clk (clk),
.rst_n (rst_n),
// APB4
.p_paddr (paddr),
.p_psel (psel),
.p_penable (penable),
.p_pwrite (pwrite),
.p_pwdata (pwdata),
.p_prdata (prdata),
.p_pready (pready),
// Safety
.err_clear (1'b0),
.err_valid (err_valid),
.err_code (err_code)
);Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.
Where it fits
Typically deployed in multi-core compute clusters that need cache coherency with a defensible ordering proof.
Why license it, not build it
Interested in AXI4-to-CHI Retaining-Cache RN-F Bridge?
Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.
Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.
circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space