Avionics, Space & Mil-Std Networking

CCSDS TM/TC Transfer-Frame Framer

A configurable CCSDS Transfer-Frame framing engine delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

91.40%

SPFM

88.62%

LFM

PASS

FMEDA

4.2K

gates

0.1.0

version

The deliverable

What you’re licensing

A configurable CCSDS Transfer-Frame framing engine delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable CCSDS Transfer-Frame framing engine delivered as synthesizable SystemVerilog soft-IP.

Key Features

TM transmit framer (CCSDS 132.0-B): assembles the 6-byte primary header (SCID, VCID, OCF, master/virtual-channel frame counts), the payload, and a CRC-16-CCITT FECF, streamed byte-serial with tm_sop/tm_eop framing
TC receive deframer (CCSDS 232.0-B): hunts the CCSDS 231.0-B Attached Sync Marker (0x1ACFFC1D), parses the 5-byte primary header, and accepts/rejects each frame on its CRC-16 FECF, routing the VCID of every accepted command (tc_accept/tc_vcid)
Shared CRC-16-CCITT core: one crc16_ccitt_byte function drives both the TM FECF the framer writes and the TC FECF the deframer checks, so the accumulation is provably identical (formally verified purity property)
Per-VC frame counting: eight virtual-channel frame counters plus a master-channel counter auto-increment as TM frames are emitted
ASIL-B safety overlay: even-parity config-register protection (err_code 1), a complementary-DMR shadow on both frame FSMs (err_code 9), and a rejected/corrupt TC frame reported as a protocol fault (err_code 3), all latched by one shared safety_monitor
Measured ISO 26262 metrics: SPFM 91.40%, LFM 88.62%, PMHF 6.80×10⁻⁹/h — PASS against the ASIL-B target with margin on every metric
Honest MVP scope: Reed-Solomon (255,223) coding, pseudo-randomization, and AOS frames are deferred, not implemented — the data-field byte stream is the documented insertion point for them

Standards & Compliance

CCSDS 132.0-B (TM Space Data Link Protocol); CCSDS 232.0-B (TC Space Data Link Protocol); CCSDS 231.0-B (TC Synchronization and Channel Coding, Attached Sync Marker); CRC-16-CCITT FECF; ISO 26262 ASIL-B SEooC (SPFM 91.40%, LFM 88.62%, PMHF 6.80×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.40% · LFM 88.62% · PASS

ISO 26262-5 FMEDA method (transferable evidence for the ECSS-Q-ST-60 / radiation case) · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	0x04 STATUS 0x08 TM_CFG 0x0C TM_DATA 0x10 TM_LEN
`0x14`	TC_STAT	0x18 IER 0x1C ISR(W1C) 0x20 ERR(W1C) [6:4]tx_state [9:7]rx_state [17:10]tc_vcid (last accepted)

Getting Started

// Minimal instantiation
ccsds #(
  .ADDR_W(6)
) u_ccsds (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in avionics, defense, and space systems built to the ARINC, MIL-STD, and CCSDS standards.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CCSDS TM/TC Transfer-Frame Framer?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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