Bus Bridges & Interconnect

Dual-Clock Async FIFO (cdc_fifo)

Cummings-style gray-pointer dual-clock async FIFO — the catalog’s foundational wide-bus CDC primitive, ASIL-A SEooC.

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ASIL-A

target

6.30%

SPFM

85.00%

LFM

PASS

FMEDA

392

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Dual-Clock Async FIFO (cdc_fifo) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Cummings-style gray-pointer dual-clock async FIFO — the catalog’s foundational wide-bus CDC primitive, ASIL-A SEooC. It is delivered as a licensable soft-IP block engineered as an ASIL-A Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A dual-clock (asynchronous) FIFO delivered as synthesizable SystemVerilog soft-IP — the canonical safe structure for moving a multi-bit data bus between two unrelated clocks using Cummings-style gray-coded read/write pointers, so the wide bus is never per-bit synchronized and full/empty can never be mis-computed from a torn sample.

Key Features

Gray-coded write/read pointers cross the clock boundary through a KEEP-attributed 2-FF synchronizer each way — never the wide data bus itself
One-bit-per-step gray encoding guarantees a mid-transition sample resolves to the old or new pointer value, never a corrupt intermediate, so wr\_full/rd\_empty are always legal
Explicit, non-silent overflow: a write while wr\_full is dropped (never overwrites live data) and surfaced on !wr\_ready, not swallowed
First-word fall-through (FWFT) read: rd_data continuously presents the head word whenever rd_valid is set
Independent per-domain active-low async reset (wr_rst_n/rd_rst_n) — no shared reset tree required between write and read domains
Formally proven gray-pointer invariants (formal/cdc\_fifo.sby: consistency, one-bit-step, legal-gray stages, no overflow/underflow, single-slot data integrity) plus clean tools/cdc\_check sign-off (rules A4/A5)
The shared mechanism underneath width\_cdc\_bridge (ASIL-B, adds ECC/DMR/err_code) and the dp\_link/dsi\_host video datapaths

Standards & Compliance

ISO 26262 ASIL-A SEooC (SPFM 6.30%, LFM 85.00%, PMHF 6.92×10⁻⁹/h); formally verified gray-pointer CDC (SymbiYosys BMC)

Functional Safety

ASIL-A (SEooC) · SPFM 6.30% · LFM 85.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
cdc_fifo #(
 .ADDR_W(6)
) u_cdc_fifo (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in heterogeneous SoCs that mix AMBA and TileLink IP and need clean, verified protocol and clock-domain crossings.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Dual-Clock Async FIFO (cdc_fifo)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space