CHI Interconnect & Coherency

CHI Slave Node

chisnf is the CHI Slave Node (SN-F) memory endpoint that completes the coherent CHI node triad the catalog already ships (RN-F – HN-F – SN-F): it…

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ASIL-B

target

91.98%

SPFM

90.30%

LFM

PASS

FMEDA

4.1K

gates

0.1.0

version

The deliverable

What you’re licensing

chisnf is the CHI Slave Node (SN-F) memory endpoint that completes the coherent CHI node triad the catalog already ships (RN-F – HN-F – SN-F): it… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

chi_sn_f is the CHI Slave Node (SN-F) memory endpoint that completes the coherent CHI node triad the catalog already ships (RN-F -> HN-F -> SN-F): it terminates the tagged memory-side port a CHI Home Node drives and bridges it to a downstream memory controller with end-to-end SECDED.

Key Features

End-to-end SECDED memory endpoint: ecc_pkg::ecc_enc64 encodes every 64-bit sub-word of the 256-bit line on write, ecc_dec64 corrects single-bit / flags double-bit upsets on read (err_code 2)
Multi-outstanding reads: up to N_OUT (default 8) reads tracked in a tagged FIFO, each returned in issue order paired with its originating TxnID; writes are posted (accept = retirement, no separate completion signal)
Direct mem_* mirror of chi_hn_f’s memory-side master port (ADDR_W=44, DATA_W=256) — plugs into the catalog’s coherent_fabric_v3/v4 tops with no adapter
Silicon-complete downstream chain via sn_to_lpddr5 (256<->64 AXI4 burst adapter) into the real lpddr5_ctrl memory controller and its DFI PHY
Request-address even parity, continuously re-checked at rest while a read is outstanding (err_code 1); downstream bus error surfaced as a fault AND propagated to the HN as a CHI read error (err_code 3)
Outstanding-read watchdog, default 4096 cycles (err_code 4); outstanding-FIFO write-pointer complementary diverse-DMR shadow (err_code 9)
Catalog FMEDA: SPFM 91.98%, LFM 90.30%, PMHF 7.03×10⁻⁹/h, PASS ASIL-B; formal bmc (pointer-DMR clean, no FIFO overflow, tagged-return invariant) + cover (multi-outstanding reachable)

Standards & Compliance

Arm AMBA 5 CHI (Issue E, SN-F memory-side role); ISO 26262 ASIL-B SEooC (SPFM 91.98%, LFM 90.30%, PMHF 7.03×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.98% · LFM 90.30% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN (accept requests)
`0x0C`	STATUS	RO [0]=busy (reads in flight) [3:1]=fifo occupancy [6:4]=err_code[2:0] [7]=err_valid

Getting Started

// Minimal instantiation
chi_sn_f #(
  .ADDR_W(6)
) u_chi_sn_f (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in multi-core compute clusters that need cache coherency with a defensible ordering proof.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CHI Slave Node?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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