RISC-V Cores & SoC Platform

RISC-V CLIC (Core-Local Interrupt Controller)

Vectored, preemptive RISC-V CLIC with a fixed one-cycle request latency and triple-layered interrupt-integrity checking, ASIL-B.

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ASIL-B

target

93.00%

SPFM

99.00%

LFM

PASS

FMEDA

939

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

RISC-V CLIC (Core-Local Interrupt Controller) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Vectored, preemptive RISC-V CLIC with a fixed one-cycle request latency and triple-layered interrupt-integrity checking, ASIL-B. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A RISC-V CLIC (Core-Local Interrupt Controller) delivered as synthesizable SystemVerilog soft-IP.

Key Features

Per-interrupt CLICINTIE enable, CLICINTIP pending, 4-bit CLICINTCTL level/priority and CLICINTATTR vectored attribute; NUM_IRQ parameterizable, v0.1 tested to 8
Fixed one-cycle request latency: pending is the only registered stage, arbitration is fully combinational off it, so a synchronized source reaches irq_req deterministically — an FTTI-analyzable constant, not a polling loop
Highest-level arbitration with highest-id tie-break (CLIC spec precedence); CLICCLAIM read returns the winning id and atomically clears its pending bit, re-pending next cycle if the level line is still asserted
Level-based preemption via CLICMTH machine threshold — only interrupts strictly above threshold are eligible; software raises CLICMTH on ISR entry and restores it on exit to nest correctly
ASIL-B: pending latch + arbitration carry a complementary DMR shadow (err_code 9, pend_t == ~pend_c)
ASIL-B: per-interrupt even parity over the level/enable/attr/threshold routing table catches an in-nibble upset a whole-register parity bit would miss (err_code 1)
ASIL-B: threshold/level plausibility check on the arbitration output (err_code 3) plus lvl_fi_i/pend_fi_i/sel_fi_i DFT injection hooks exercise each mechanism

Standards & Compliance

RISC-V CLIC (Core-Local Interrupt Controller) specification, AMBA APB4-lite; ISO 26262 ASIL-B SEooC

Functional Safety

ASIL-B (SEooC) · SPFM 93.00% · LFM 99.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CLICCFG	config (RW; nlbits etc — stored, informational in v0.1)
`0x04`	CLICINTIP	per-IRQ pending [NUM_IRQ-1:0] RO
`0x08`	CLICINTIE	per-IRQ enable [NUM_IRQ-1:0]
`0x0C`	CLICINTATTR	per-IRQ vectored attr [NUM_IRQ-1:0] (bit i = vectored)
`0x10`	CLICINTCTL	4 bits/IRQ packed level/priority (0 = lowest)

…2 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
clic #(
 .ADDR_W(6)
) u_clic (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in RISC-V CLIC (Core-Local Interrupt Controller)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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