Cryptography & Data Integrity

Programmable CRC Accelerator (crc)

Byte-serial, multi-polynomial CRC engine that offloads AUTOSAR E2E-profile integrity checks from software to a single self-checked hardware primitive.

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ASIL-B

target

100.00%

SPFM

100.00%

LFM

PASS

FMEDA

2.4K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Programmable CRC Accelerator (crc) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Byte-serial, multi-polynomial CRC engine that offloads AUTOSAR E2E-profile integrity checks from software to a single self-checked hardware primitive. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A programmable multi-polynomial CRC accelerator delivered as synthesizable SystemVerilog soft-IP, covering CRC-8/16/32 in one engine — including the exact AUTOSAR CRC-8, CRC-8H2F, CRC-16, CRC-32, and CRC-32P4 variants that AUTOSAR E2E protection profiles rely on.

Key Features

Fully runtime-programmable CRC model — POLY, INIT, XOROUT, and CTRL.REFLECT (LSB-first/MSB-first) — one engine covers CRC-8/16/32 and any custom polynomial
Bit-exact AUTOSAR CRC library coverage (CRC-8, CRC-8H2F, CRC-16, CRC-32, CRC-32P4) — the five variants AUTOSAR E2E Profiles draw on, offloaded from software to one clock cycle per byte
Table-free, fully parallel combinational fold: one byte per clock, one 32-bit word every 4 cycles, no lookup tables, no pipeline stalls
CRC (0x18) reads back the finalized result with XOROUT applied; RAW (0x1C) reads the bare running register for incremental/split-message hashing across DMA-scattered buffers
ASIL B complementary-shadow DMR on the running CRC register: a hardware fault in the offloaded computation is caught in-cycle (err_code 9), never silently returned as a valid result
ASIL B even parity on POLY/INIT/XOROUT/CTRL config registers (err_code 1) protects the CRC model itself from storage corruption
Catalog FMEDA: SPFM 100.00%, LFM 100.00%, PMHF 3.36×10⁻⁹/h — PASS against ASIL-B, at 2,377 cells (smallest IP in the security/integrity bundle)

Standards & Compliance

IEEE 802.3, ITU-T CRC-16-CCITT, AUTOSAR CRC library (Crc.h) as used by AUTOSAR E2E Profiles; ISO 26262 ASIL B SEooC (SPFM 100.00%, LFM 100.00%, PMHF 3.36×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 100.00% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=REFLECT (1=LSB-first/right-shift, 0=MSB-first/left-shift)
`0x04`	POLY	generator polynomial (write in the form matching REFLECT)
`0x08`	INIT	initial register value 0x0C XOROUT final output XOR
`0x10`	CMD	W1: [0]=RESET (crc <- INIT) 0x14 DATA write byte[7:0] -> fold one byte
`0x18`	CRC	RO: crc ^ XOROUT (result) 0x1C RAW RO: bare crc register

Getting Started

// Minimal instantiation
crc #(
 .ADDR_W(6)
) u_crc (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Programmable CRC Accelerator (crc)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space