Timers, Clocks & I/O

Clock-Reset-Power Controller

crg is a clock-reset-generator / power-management controller (CRG/PMU) for a safety SoC,

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ASIL-B

target

99.00%

SPFM

95.00%

LFM

PASS

FMEDA

782

gates

1.0.0

version

The deliverable

What you’re licensing

crg is a clock-reset-generator / power-management controller (CRG/PMU) for a safety SoC, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

crg is a clock-reset-generator / power-management controller (CRG/PMU) for a safety SoC, delivered as synthesizable SystemVerilog soft-IP with an APB4-lite control interface and built-in ISO 26262 (ASIL-B) safety instrumentation.

Key Features

Per-domain clock-enable + glitch-free gating
Ordered reset sequencer + reset-cause capture
Power-mode handshake + ack timeout (\rightarrow) err_code 4
Reset-sequencer + power-state FSM DMR (err_code 9)
Illegal-transition plausibility (err_code 3) + config parity (err_code 1)
Pairs with pll_guard / clk_mon

Standards & Compliance

ISO 26262 (SEooC)

Functional Safety

ASIL-B (SEooC) · SPFM 99.00% · LFM 95.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CR	[1]=SEQ_GO (write 1: launch the reset deassert sequence) [0]=SEQ_EN (sequencer enable)
`0x04`	SEQHOLD	per-domain reset hold count, HOLD_W bits per domain, packed LSB=domain0
`0x08`	TIMEOUT	reference cycles a domain may take to pwr_ack / be sequenced before err_code 4
`0x0C`	PWRCR	[1:0]=PWR_REQ requested power mode (0=RUN 1=SLEEP 2=DEEP_SLEEP)
`0x10`	STAT	[0]=SEQ_BUSY [1]=SEQ_DONE(W1C) [2]=TMO_F(W1C) [3]=ILL_F(W1C) [7:4]=reset-cause one-hot reset cause: [4]=POR [5]=WDOG…

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
crg #(
  .ADDR_W(6)
) u_crg (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the housekeeping layer every SoC needs — timing, watchdogs, reset, and I/O.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Clock-Reset-Power Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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