Motor, Power & Sensor Control

Push-Pull DC-DC Converter Controller

APB4 push-pull DC-DC gate-timing controller with OC/OV/trip supervision and a structural safe-state — ASIL-D SEooC.

Request this IP →Browse the catalog

ASIL-D

target

100.00%

SPFM

100.00%

LFM

PASS

FMEDA

2.3K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Push-Pull DC-DC Converter Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

APB4 push-pull DC-DC gate-timing controller with OC/OV/trip supervision and a structural safe-state — ASIL-D SEooC. It is delivered as a licensable soft-IP block engineered as an ASIL-D Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

APB4 digital controller for a dual-FET push/pull DC-DC converter (center-tapped transformer primary), with ASIL-D safety.

1. Key Features

Push-pull alternate-half gate drive (gate_a/gate_b) off a single carrier — structurally mutually exclusive, no cross-conduction / transformer flux walk
Programmable dead-time (DEADTIME) and duty limit (DUTY ≤ PERIOD−DEADTIME), with a soft-start ramp (SOFTSTART) that steps the effective duty up from 0 to limit inrush
Over-current protection with leading-edge blanking (LEB, rejects the turn-on spike) and an N-cycle glitch filter (FILT); cycle-by-cycle termination or CTRL.OC_LATCH latched fault
Over-voltage (ov) and an async hard trip_n (UVLO / desat / watchdog) always latch a fault and force both gates off; FAULTCLR only accepted once oc/ov/trip_n are released
Config-register parity across CTRL/PERIOD/DUTY/DEADTIME/SOFTSTART/LEB/FILT — err_code 1
ASIL-D lockstep: independent-DMR carrier + diverse on-window comparator, plus antivalent shadows on the phase select, soft-start limit, fault/oc_term latches, and OC/OV/trip synchronisers — err_code 9
APB4 slave register interface with IER/ISR interrupt (dcdc_irq) on OC or FAULT events

Standards & Compliance

IEC 62477-1 (power electronic systems); ISO 26262 ASIL-D SEooC (SPFM 100.00%, LFM 100.00%, PMHF 0/h, measured)

Functional Safety

ASIL-D (SEooC) · SPFM 100.00% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN [1]=OC_LATCH (OC latches a fault vs cycle-by-cycle)
`0x04`	STATUS	[0]=FAULT [1]=OC_ACTIVE [2]=PHASE (B half) [3]=SOFTSTARTING [4]=RUNNING (RO)
`0x08`	PERIOD	half-period in clocks 0x0C DUTY on-time in clocks (<= PERIOD-DEADTIME)
`0x10`	DEADTIME	cycles at each half start before the gate turns on
`0x14`	SOFTSTART	clocks per soft-start duty-limit step (+1 each step until DUTY)

…4 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
dcdc_pp #(
 .ADDR_W(6)
) u_dcdc_pp (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in motor drives, power conversion, and sensor front-ends in automotive and industrial systems.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Push-Pull DC-DC Converter Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space