System, Safety & Compute

ECC SRAM Controller

ASIL-B SECDED SRAM controller with background scrubbing and optional address-decode aliasing detection for automotive/aerospace on-chip memories.

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ASIL-B

target

93.01%

SPFM

100.00%

LFM

PASS

FMEDA

1.3K

gates

0.1.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

ASIL-B SECDED SRAM controller with background scrubbing and optional address-decode aliasing detection for automotive/aerospace on-chip memories. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

ecc_sram is an ASIL-B SECDED (Single-Error Correct, Double-Error Detect) SRAM controller, delivered as synthesizable SystemVerilog, that wraps any external 32-bit-wide SRAM macro with a 7-bit code (ecc_pkg::ecc_enc / ecc_pkg::ecc_dec): single-bit errors are corrected transparently on read, and double-bit errors are flagged through the catalog safety monitor (err_code = 1).

Key Features

SECDED per 32-bit word (7 check bits): every single-bit error corrected transparently, every double-bit error detected → err_code 1, ded_count, last_err_addr.
Background scrub FSM (scrub_en) walks the array on host-idle cycles and writes back any corrected word before a second bit error can turn it uncorrectable.
Optional address-decode aliasing check (ADDR_PARITY=1): a per-row address signature catches a wrong-row read that data SECDED alone cannot see → addr_err_count, err_code 1; formally proved and fault-injection verified.
DFT fault-injection port (fi_req/fi_addr/fi_mask) XORs an arbitrary mask into the stored data, ECC bits, or address signature for ISO 26262 diagnostic-coverage proof by test.
Data-plane-only interface: no APB/AXI configuration slave; every signal (h_, scrub_en, fi_, counters, err_valid/err_code) is a plain wire.
Parameterised address width (AW, default 10 → 1K words) with fixed 32-bit data width (DW fixed by the ecc_pkg codec).
ASIL-B catalog safety-monitor interface (err_clear/err_valid/err_code[3:0]); passes SPFM 93.01%, LFM 100.00%, PMHF 9.05×10⁻⁹ /h.

Standards & Compliance

ISO 26262:2018 Part 5, ASIL B (SEooC) — SPFM/LFM/PMHF per Annex C; SECDED (Hamming-derived, single-error-correct / double-error-detect) memory protection.

Functional Safety

ASIL-B (SEooC) · SPFM 93.01% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
ecc_sram #(
 .ADDR_W(6)
) u_ecc_sram (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in ECC SRAM Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space