Serial, Networking & Storage

Automotive T1 Ethernet MAC (eth\_t1\_mac)

etht1mac is the digital MAC frame layer of an automotive single-pair-Ethernet (SPE) port.

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ASIL-B

target

93.05%

SPFM

90.00%

LFM

PASS

FMEDA

4.4K

gates

1.0.0

version

The deliverable

What you’re licensing

etht1mac is the digital MAC frame layer of an automotive single-pair-Ethernet (SPE) port. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

eth_t1_mac is the digital MAC frame layer of an automotive single-pair-Ethernet (SPE) port. It implements IEEE 802.3 transmit/receive framing for the three T1 PHY families — 100BASE-T1, 1000BASE-T1, and 10BASE-T1S — and exposes an APB4-lite slave for configuration and frame data.

Key Features

One shared IEEE 802.3 TX/RX frame engine (preamble + SFD + CRC-32 FCS) reused across 100BASE-T1, 1000BASE-T1, and 10BASE-T1S via MAC_CTRL.MODE, with a 48-bit MAC-address filter (unicast / broadcast / promiscuous)
10BASE-T1S PLCA transmit-opportunity gating: PLCA_ID/PLCA_NCNT node config, a queued TX_GO that waits for the plca_to_i grant pulse, a live PLCA_STAT transmit-opportunity counter, and a TO_TIMEOUT watchdog → err_code 4 on a lost/stuck token
RX CRC-32 FCS verification plus frame-length plausibility (>=1 payload byte, <= MAX_FRAME) → err_code 3, discarding runt/oversize or corrupted frames before they reach the host
SECDED-protected TX/RX frame buffers (fifo_ecc, single-bit corrected in-line, double-bit → err_code 2) accessed as programmed I/O (TX_DATA/RX_DATA byte push/pop) — no burst DMA master, so FIFO_BYTES and host polling cadence are sized to the port’s frame/burst profile
Single fabric clock domain across the xMII boundary with no internal CDC logic — a PHY adapter presenting rxd/rx_valid on its own recovered clock must bridge before this MAC (confirmed in the CDC sign-off catalog)
ASIL-B safety: config-register parity (err_code 1), frame-buffer SECDED DBE (err_code 2), CRC-32/length protocol fault (err_code 3), PLCA transmit-opportunity timeout (err_code 4), complementary-DMR RX-error FSM lockstep (err_code 9), all through one shared safety_monitor
DFT fault injection (FI_CTRL: fi_cfg_par, fi_rx_dbe, fi_to_tmo, fi_fsm_dmr) exercises every safety mechanism from firmware without external fault hardware

Standards & Compliance

IEEE 802.3 (Ethernet MAC framing, CRC-32 FCS); IEEE 802.3bw/802.3bp (100BASE-T1 / 1000BASE-T1, external PHY); IEEE 802.3cg Clause 148 (10BASE-T1S + PLCA, external PHY reconciliation sublayer); ISO 26262 ASIL-B SEooC (SPFM 93.05%, LFM 90.00%, PMHF 5.79×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 93.05% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	MAC_CTRL	[0]=TX_EN [1]=RX_EN [2]=PROMISC [4:3]=MODE(0=100T1 1=1000T1 2=10T1S) [5]=PLCA_EN
`0x04`	MAC_STAT	RO [0]=TX_BUSY [1]=RX_FIFO_NE [2]=RX_ERR [3]=RX_FIFO_FULL [4]=TX_PEND [5]=TO_TMO
`0x08`	TX_DATA	W byte-push into TX FIFO
`0x0C`	TX_GO	W: write the payload length (bytes) and start TX (preamble+SFD+payload+CRC)
`0x10`	RX_DATA	R byte-pop from RX FIFO (SECDED-corrected)

…7 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
eth_t1_mac #(
  .ADDR_W(6)
) u_eth_t1_mac (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Automotive T1 Ethernet MAC (eth\_t1\_mac)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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