Motor, Power & Sensor Control

Fan Tachometer & Stall Supervisor

APB4 fan tach/PWM controller that turns a cooling-fan pulse into an autonomous, hardware-latched stall fault — ISO 26262 ASIL-B SEooC.

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ASIL-B

target

93.00%

SPFM

90.00%

LFM

PASS

FMEDA

1.6K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Fan Tachometer & Stall Supervisor routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

APB4 fan tach/PWM controller that turns a cooling-fan pulse into an autonomous, hardware-latched stall fault — ISO 26262 ASIL-B SEooC. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

fan_sensor reads a fan tachometer to report speed (period + cumulative edge count), flags a stalled fan, and—for 4-wire fans—generates the PWM control signal.

Key Features

Direct tachometer period + cumulative edge-count measurement (TACH_PERIOD/TACH_COUNT) via a 2-FF-synchronized rising-edge detector on the open-collector tach_in line
Autonomous hardware stall detection: STALL_TIMEOUT (0 = disabled) latches STATUS.stall and err_code 4 with no host polling required
4-wire PWM speed-control output (PWM_PERIOD/PWM_DUTY), auto-disabled (pwm_out forced low) in 3-wire mode via CTRL.MODE
Per-edge and per-stall interrupt (fan_irq), maskable via IER
Config-register even parity on CTRL (err_code 1)
Independent-DMR (complementary-redundant) shadow of the primary tach/stall pulse counter (err_code 9)
FMEDA-verified: SPFM 93.00%, LFM 90.00%, PMHF 2.05×10⁻⁹/h — ASIL-B PASS

Standards & Compliance

AMBA APB4 (ARM IHI 0024); 4-wire PWM fan-control convention (~25 kHz carrier); ISO 26262 ASIL-B SEooC (SPFM 93.00%, LFM 90.00%, PMHF 2.05×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 93.00% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN [1]=MODE(0=4w,1=3w) [2]=PWM_EN 0x04 PWM_PERIOD 0x08 PWM_DUTY
`0x0C`	TACH_PERIOD(RO)	0x10 TACH_COUNT(RO) 0x14 STALL_TIMEOUT
`0x18`	STATUS	[0]=stall [1]=tach_valid [2]=spinning (RO) 0x1C IER

Getting Started

// Minimal instantiation
fan_sensor #(
 .ADDR_W(6)
) u_fan_sensor (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in motor drives, power conversion, and sensor front-ends in automotive and industrial systems.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Fan Tachometer & Stall Supervisor?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space