Block diagram
Physical implementation
What you’re licensing
ISO 17458 / FlexRay 3.0.1 dual-channel static-segment TT controller, ASIL-B. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:
What it is
flexray is an ISO 17458 / FlexRay 3.0.1 time-triggered communication controller (TT-CC): a synthesizable SystemVerilog protocol engine for the dual-channel (A/B) TDMA static segment, with an APB4-lite slave register interface and built-in ASIL-B safety instrumentation.
Key Features
- Dual-channel (A/B) static-segment TDMA engine: 0..63 cycle counter × 0..63 slot counter against a configurable MAX_SLOTS schedule RAM
- Channel-redundant transmit — cha_txd/chb_txd mirror the same bit; receive selects one channel (A priority, else B) — no in-RTL cross-channel vote
- 11-bit header-CRC (poly 0x385) + 24-bit frame-CRC (poly 0x5D6DCB) generate/check plus slot/cycle/length plausibility → err_code 3
- SECDED-protected RX frame buffer (fifo_ecc): single-bit corrected transparently, double-bit uncorrectable → err_code 2
- Programmable loss-of-sync timeout watchdog (SYNC_TIMEOUT) → err_code 4; even-parity config-register protection → err_code 1
- KEEP_ATTR complementary-DMR lockstep on the protocol FSM and slot/cycle counters → err_code 9, with fi_* DFT fault-injection on every mechanism
- External TJA1080-class bus driver per channel; cha_bus_active/chb_bus_active feed an external bus-guardian / active-star function (not implemented on-chip)
Standards & Compliance
ISO 17458 / FlexRay 3.0.1; ISO 26262 ASIL-B SEooC (SPFM 94.05%, LFM 90.00%, PMHF 9.41×10⁻⁹/h)
Functional Safety
ASIL-B target (SEooC) · SPFM 94.05% · LFM 90.00% · Informational — not gated
Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.
ISO 26262:2018 · FMEDA available · Safety Manual included
Register Map
| Offset | Register | Description |
|---|---|---|
0x00 | CTRL | [0]=POC_RUN(enable) [1]=CHA_EN [2]=CHB_EN [3]=LOOPBACK [4]=RXPOP(W1 self-clear) |
0x04 | STATUS | [0]=RX_VALID [1]=SYNC_OK [2]=IN_STATIC [5:3]=fsm_state [13:8]=cycle_cnt [14]=RX_FULL [15]=SYNC_SEEN [21:16]=slot_cnt |
0x08 | CFG | [3:0]=STATIC_SLOTS(num static slots,1..MAX) [9:4]=SLOT_TICKS(ticks/slot) [15:10]=NIT_TICKS [16]=SYNC_REQ(require a s… |
0x0C | TIMING | [15:0]=SYNC_TIMEOUT (cycles w/o a sync frame -> loss-of-sync, err4) |
0x10 | SCHED_IDX | [3:0]=slot index selected for SCHED_DAT access |
…7 more registers — see datasheet for the full table.
Getting Started
// Minimal instantiation
flexray #(
.ADDR_W(6)
) u_flexray (
.clk (clk),
.rst_n (rst_n),
// APB4
.p_paddr (paddr),
.p_psel (psel),
.p_penable (penable),
.p_pwrite (pwrite),
.p_pwdata (pwdata),
.p_prdata (prdata),
.p_pready (pready),
// Safety
.err_clear (1'b0),
.err_valid (err_valid),
.err_code (err_code)
);Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.
Where it fits
Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.
Why license it, not build it
Interested in FlexRay Dual-Channel TT Controller?
Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.
Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.
circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space