Serial, Networking & Storage

I²C Master Controller

A configurable I²C master controller delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

97.00%

SPFM

100.00%

LFM

PASS

FMEDA

2.5K

gates

1.6.0

version

The deliverable

What you’re licensing

A configurable I²C master controller delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable I²C master controller delivered as synthesizable SystemVerilog soft-IP. It implements the full I²C master protocol (START, repeated-START, data transfer, STOP) on an APB4 register interface, with parameterized TX/RX FIFOs and built-in ASIL B safety instrumentation (config-register parity, FSM/datapath complementary-DMR lockstep, SECDED-protected FIFOs).

Key Features

Standard-mode (100 kHz), Fast-mode (400 kHz), and Fast-Plus (1 MHz) via the 16-bit PRER half-period divisor (NXP UM10204 compliant); 9-state quarter-period FSM (IDLE→START→ADDR→DATA_TX/RX→ACK_TX/RX→STOP)
Open-drain i2c_scl_o/i2c_sda_o (drive-low only) — no internal pull-up or bus-loading model; pull-up sizing and termination are the integrator’s board design
No clock stretching: bit timing is free-running and never gates on a sampled-low SCL — only attach slaves that release the clock inside the PRER window
Hardware bus recovery: SR.STUCK flags a slave holding SCL/SDA low while idle; BBCR.RECOVER drives 9 SCL pulses plus a STOP to free it, with a bit-bang override (BBCR.BB_EN) for firmware-driven recovery
Arbitration-loss detection (SR.AL) every bit, slave-NACK handling (SR.NACK) with CR2.NACK_LAST for correct read termination, and RX-FIFO-overrun flagging (SR.OVR)
SECDED-ECC-protected TX/RX FIFOs (fifo_ecc, 4–64 deep) — single-bit upsets auto-corrected, double-bit → err_code 2
ASIL-B: config-register (CR/PRER/CR2/BBCR) even parity → err_code 1; diverse-DMR complementary lockstep on the FSM and shift register → err_code 9; shared safety_monitor aggregation

Standards & Compliance

NXP I²C-bus Specification UM10204 Rev. 7 (Standard/Fast/Fast-Plus master mode); ISO 26262 ASIL-B SEooC (SPFM 97.00%, LFM 100.00%, PMHF 1.40×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 97.00% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CR:	[7]=EN [1]=TXEIE [0]=RXNEIE
`0x04`	PRER:	[15:0] SCL half-period in clk cycles (SCL period = 2×PRER; 0=off)
`0x08`	DR:	write=push TX FIFO (byte to send); read=pop RX FIFO
`0x0C`	SR:	[6]=STUCK [5]=BSY [4]=AL [3]=OVR [2]=NACK [1]=RXNE [0]=TXE (read-only)
`0x10`	CR2:	[7]=START [6]=STOP [5]=NACK_LAST [4]=RD_WRN [3:0]=NBYTES (1-15; 0=15)

…1 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
i2c_master #(
  .ADDR_W(6)
) u_i2c_master (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in I²C Master Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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