Serial, Networking & Storage

MIPI I3C Master (SDR)

APB4-mapped MIPI I3C master supporting SDR (Single Data Rate) transfer mode per MIPI I3C v1.1.1.

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ASIL-B

target

90.75%

SPFM

89.23%

LFM

PASS

FMEDA

1.1K

gates

2.33.0

version

The deliverable

What you’re licensing

APB4-mapped MIPI I3C master supporting SDR (Single Data Rate) transfer mode per MIPI I3C v1.1.1. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

APB4-mapped MIPI I3C master supporting SDR (Single Data Rate) transfer mode per MIPI I3C v1.1.1. Handles ENTDAA address assignment, Common Command Codes (CCCs) and private SDR write/read transfers.

Key Features

MIPI I3C SDR master — private write/read transfers
ENTDAA dynamic address assignment
Common Command Codes (CCC): SETMRL, GETPID, RSTDAA
Diverse-DMR FSM lockstep (err_code 9)
Config-register parity (err_code 1)
APB4 slave CSR + interrupt on transfer complete

Standards & Compliance

MIPI I3C Specification v1.1.1 (SDR mode)

Functional Safety

ASIL-B (SEooC) · SPFM 90.75% · LFM 89.23% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN [1]=RNW 0x04 ADDR [6:0] 0x08 TXDATA 0x0C RXDATA
`0x10`	CMD	(write 1 = start transfer) 0x14 STATUS [0]=BUSY [1]=DONE [2]=ACK [3]=RX_READY

Getting Started

// Minimal instantiation
i3c_master #(
  .ADDR_W(6)
) u_i3c_master (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in MIPI I3C Master (SDR)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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