Serial, Networking & Storage

JESD204B Link + Transport Receiver

JESD204B link/transport-layer receiver for payload-ADC ingest — CGS/ILAS/lane-align above an external SERDES/PHY, ASIL-B.

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ASIL-B

target

90.38%

SPFM

89.93%

LFM

Informational

FMEDA

1.6K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

JESD204B Link + Transport Receiver routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

JESD204B link/transport-layer receiver for payload-ADC ingest — CGS/ILAS/lane-align above an external SERDES/PHY, ASIL-B. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

jesd204_rx is the JESD204B link + transport-layer receiver for high-speed payload-ADC / data-converter ingest, delivered as synthesizable SystemVerilog soft-IP with an APB4-lite control interface and built-in ISO 26262 (ASIL-B) safety instrumentation.

Key Features

Code Group Sync (CGS): cross-lane-agreed run of 4 consecutive /K28.5/ commas, bounded by a SYNC_TIMEOUT comma-acquisition watchdog → err_code 4
Initial Lane Alignment Sequence (ILAS): tracks 4 /R..Q..A/ multiframes and captures the JESD config word (DID/BID/LID/L/M) from the 2nd multiframe into CFG_ID
Per-multiframe lane alignment to the /A/ (K28.3) marker; a cross-lane disagreement or stray DATA-phase control character is flagged as a fault, never silently corrected
Fixed-latency, unbuffered deframe: octet-in-frame (mod F) / frame-in-multiframe (mod K) counters drive rx_sample_o / _valid_o / _frame_start_o / _multiframe_o with no elastic FIFO on the datapath
ASIL-B safety: config-register parity (err_code 1), 8b/10b + ILAS-config + lane-align protocol aggregate (err_code 3), CGS acquisition timeout watchdog (err_code 4), KEEP_ATTR diverse-DMR lockstep on the link FSM + frame/multiframe counters (err_code 9)
Per-lane decoded-symbol interface (8-bit character + K-char flag + external code-error flag) partners with any vendor JESD204B SERDES/PHY — GTH/GTY-class transceiver or discrete SerDes + 8b/10b
FI_CTRL DFT fault-injection register (fi_parity / fi_align / fi_timeout / fi_lockstep) exercises every safety mechanism on the bench and in a fault campaign

Standards & Compliance

JEDEC JESD204B (link + transport layer only, 8b/10b — not JESD204C); ISO 26262 ASIL-B SEooC (SPFM 90.38%, LFM 89.93%, PMHF 2.98×10⁻⁹/h, Technology Preview / informational)

Functional Safety

ASIL-B target (SEooC) · SPFM 90.38% · LFM 89.93% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN, [1]=SUBCLASS, [4:2]=LANES_M1, [7:5]=F_M1, [12:8]=K_M1, [13]=SOFT_RST
`0x04`	STATUS	RO [1:0]=LINK_STATE, [2]=CGS_DONE, [3]=ILAS_DONE, [4]=CFG_CAPTURED, [5]=ALIGNED, [6]=SYNC_REQ, [7]=ERR_8B10B, [8]=ER…
`0x08`	INTR	W1C [0]=SYNC_DONE, [1]=ILAS_DONE, [2]=ERR_PROTO, [3]=ERR_TIMEOUT
`0x0C`	INTR_EN	RW same bits
`0x10`	CFG_ID	RO captured ILAS config [7:0]=DID, [11:8]=BID, [16:12]=LID, [20:17]=L_M1, [28:21]=M_M1

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
jesd204_rx #(
 .ADDR_W(6)
) u_jesd204_rx (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in JESD204B Link + Transport Receiver?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space