RISC-V Cores & SoC Platform

JTAG DTM (RISC-V Debug Transport Module)

IEEE 1149.1 TAP + RISC-V Debug Transport Module bridging JTAG to a Debug Module Interface bus…

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ASIL-B

target

92.75%

SPFM

90.00%

LFM

PASS

FMEDA

1.3K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

JTAG DTM (RISC-V Debug Transport Module) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

IEEE 1149.1 TAP + RISC-V Debug Transport Module bridging JTAG to a Debug Module Interface bus… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A JTAG TAP controller and RISC-V Debug Transport Module: a 16-state IEEE 1149.1 TAP FSM that carries the RISC-V DMI (Debug Module Interface) register — IDCODE/DTMCS/DMI/BYPASS over tck — and bridges it to a downstream Debug Module across a tck↔︎clk CDC handshake, with an ASIL-B safety overlay and a hardware debug-authorization gate.

Key Features

16-state IEEE 1149.1 TAP FSM (tck domain) with IR: BYPASS(0x00)/IDCODE(0x01)/DTMCS(0x10)/DMI(0x11)/BYPASS(0x1F); TEST-LOGIC-RESET forces IR back to IDCODE
Hardware debug-authorization gate: dbg_en_i must be asserted for a DMI read/write op to reach the downstream Debug Module — gated accesses report busy rather than driving the bus, so mission-mode lockout does not depend on firmware
TAP-FSM complementary-DMR shadow (KEEP_ATTR) catches an SEU in the scan state machine before it can mis-shift into the wrong register (err_code 9)
Even parity over the captured IR and the APB config register catches a flipped instruction/config bit (err_code 1)
DMI op-plausibility + sticky protocol-error reporting: a reserved op or a returned Debug-Module failure status is never silent (err_code 3)
Bounded DMI access timeout across the tck↔︎clk CDC handshake (err_code 4), configurable via DMI_TIMEOUT
Catalog FMEDA (pre-sign-off engineering numbers): SPFM 92.75%, LFM 90.00%, PMHF 1.72×10⁻⁹/h — PASS against the ASIL-B target, at 1,261 generic cells

Standards & Compliance

IEEE 1149.1 (JTAG); RISC-V External Debug Support Specification (Debug Transport Module, JTAG, §6) / RISC-V Debug Module Interface v0.13/1.0; AMBA APB4-lite; ISO 26262 ASIL-B SEooC (SPFM 92.75%, LFM 90.00%, PMHF 1.72×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 92.75% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=dbg_en_soft (ANDed with dbg_en_i) [1]=dmihardreset (W1pulse) [8]=cfg_par
`0x04`	STATUS	[3:0]=tap_state(sys-synced) [5:4]=dmi_op_status [6]=dmi_busy [7]=dbg_active(RO)
`0x08`	IDCODE	[31:0]=IDCODE value (RO)
`0x0C`	IR	[4:0]=captured IR (RO, sys-synced) [8]=ir_par_err(RO)
`0x10`	DMI_ADDR	[ABITS-1:0]=last DMI address (RO)

…2 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
jtag_dtm #(
 .ADDR_W(6)
) u_jtag_dtm (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in JTAG DTM (RISC-V Debug Transport Module)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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