AI Inference & Acceleration

KVCE-Lite

The entry-tier KV-cache compression engine — the smallest, fastest-to-harden member of the KVCE family.

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ASIL-B

target

99.45%

SPFM

60.53%

LFM

PASS

FMEDA

31.5K

gates

0.1.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

The entry-tier KV-cache compression engine — the smallest, fastest-to-harden member of the KVCE family. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

Normative source: KVCE-Lite_Microarchitecture_Spec.md. This document summarizes the parameters, register map, ports, and functional behavior implemented in “rtl/.

Key Features

Recency-tiered format selection: recent tokens stay native (HOT), distant tokens go INT4 group-quantized (WARM) — 2 tiers, programmable TIER0_LIMIT threshold.
On-chip compressed page table (direct-mapped, bump allocator): maps logical (seq, layer, block) → physical {offset, length, format}, zero software bookkeeping for variable-length compressed blocks.
First-class CTRL.BYPASS mode: native KV round-trips bit-exactly — the single biggest adoption de-risker for a memory-path block.
Config-register even parity (CTRL/MEM_BASE/MEM_SIZE/TIER0_LIMIT/GROUP_CFG) → err_code 1.
Command-FIFO SECDED + pointer-DMR on the buffered 64-bit descriptor → err_code 2.
AXI SLVERR/DECERR, page-table-miss, mem-full, and bad-descriptor protocol checks, all aggregated → err_code 3.
Complementary-DMR command-sequencer FSM lockstep → err_code 9; formally proven quant↔︎dequant round-trip bound and page-table alloc/lookup invariant.

Standards & Compliance

AMBA AXI4 / AXI4-Stream / APB4; ISO 26262 ASIL-B (SEooC)

Functional Safety

ASIL-B (SEooC) · SPFM 99.45% · LFM 60.53% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
kvce_lite #(
 .ADDR_W(6)
) u_kvce_lite (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in safety-critical edge inference — ADAS, autonomous robotics, and machine vision.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Technical paper

The architecture, prior-art positioning, and integration story of this engine are set out in the open-access paper “Inline Hardware KV-Cache Compression for Long-Context Transformer Inference” (Zenodo). Detailed microarchitecture and quantitative sign-off data follow under a mutual NDA.

Interested in KVCE-Lite?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space