RISC-V Cores & SoC Platform

LPDDR5 / DFI Memory Controller (ASIL-B)

The real DRAM endpoint of the coherent-memory fabric SKU.

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ASIL-B

target

93.06%

SPFM

100.00%

LFM

PASS

FMEDA

43.7K

gates

0.1.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

The real DRAM endpoint of the coherent-memory fabric SKU. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

An ASIL-B LPDDR5 / DFI 5.x memory controller — the digital controller sitting above a DFI 5.x PHY boundary (analog PHY out of scope) — with inline data-at-rest SECDED, an independent link-ECC over the DFI transport, patrol scrub, RFM/RAA row-hammer mitigation, and a RAS/error-reporting layer feeding one shared safety_monitor.

Key Features

JEDEC-proven command engine — per-bank + global timing down-counters, formally verified CA-frame and timing-envelope safety (bmc)
Inline data-at-rest SECDED + RMW + poison-forwarding — corrected SBE telemetry, DBE → err_code 2 + AXI SLVERR
Independent link-ECC over the DFI transport + MRR write-link poll — a 2nd SECDED protecting the wire, not the array
Patrol scrub (interval/idle) + on-read auto-writeback — repairs latent single-bit upsets before a 2nd flip
RFM/RAA row-hammer mitigation — per-bank rolling-ACT accumulation at RAAIMT/RAAMMT thresholds
Command-engine diverse-DMR + config/address/reorder-buffer parity → err_code 1/2/9; shared watchdog → err_code 4
AXI4 data plane + APB4-lite CSR sidecar, multi-rank chip-select, optional TileLink-UH front-end (lpddr5_ctrl_tl_top)

Standards & Compliance

JEDEC JESD209-5 (LPDDR5), JEDEC DFI 5.x; ISO 26262 ASIL-B SEooC

Functional Safety

ASIL-B (SEooC) · SPFM 93.06% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=ENABLE [2:1]=LP_REQ (0=run,1=power-down,2=self-refresh) [4:3]=FSP_REQ [5]=ECC_EN (inline data-at-rest SECDE…
`0x04`	STATUS	RO [0]=BUSY [1]=INIT_DONE [2]=ERR_VALID [6:3]=ERR_CODE [7]=REF_PENDING!=0 [9:8]=LP_STATE (0=run,1=PD,2=SR) [11:10]=…
`0x08`	T_RCD	RW ACT->column delay (clock counts; all timing CSRs are clocks)
`0x0C`	T_RP	RW PRE->ACT
`0x10`	T_RAS	RW ACT->PRE

…27 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
lpddr5_ctrl #(
 .ADDR_W(6)
) u_lpddr5_ctrl (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in LPDDR5 / DFI Memory Controller (ASIL-B)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space