Avionics, Space & Mil-Std Networking

MIL-STD-1553B Remote Terminal (RT) Controller

A configurable MIL-STD-1553B Remote Terminal (RT) controller delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

93.75%

SPFM

90.00%

LFM

PASS

FMEDA

1.3K

gates

0.1.0

version

The deliverable

What you’re licensing

A configurable MIL-STD-1553B Remote Terminal (RT) controller delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable MIL-STD-1553B Remote Terminal (RT) controller delivered as synthesizable SystemVerilog soft-IP.

Key Features

Manchester II bi-phase-L encode/decode (1 = H→L, 0 = L→H) with a programmable half-bit period (MAN_HALF = clk_Hz/2e6 for the standard 1 Mbps rate) and sync-pattern classification (command/status vs. data) by 1.5-bit-time level duration
RT protocol FSM (IDLE→RX_CMD→{RX_DATA×WC→TX_STATUS | TX_STATUS→TX_DATA×WC}) decodes RTADDR/T_R/SUBADDR/WORDCNT, answers only commands addressed to its own 5-bit RTADDR, and streams up to 32 data words per message (WORDCNT=0 decodes as 32 words per 1553B)
Dual-redundant bus inputs (bus_a_i/bus_b_i), each independently 2-FF synchronized, terminating at the decoded Manchester level — the transformer-coupled transceiver is external; v0.1 locks the receive mux to bus A at reset, with dynamic first-valid-sync arbitration slated for a later revision
Odd-parity + sync-pattern word-level fault detection funnels into the ERR register and the shared safety_monitor as err_code 3
Even-parity protection on the CTRL/RTADDR config registers reports as err_code 1
Complementary-DMR lockstep shadow on the RT protocol FSM — an independent next-state cone compared every cycle — reports any divergence as err_code 9
APB4 register map (4-byte stride): CTRL 0x00, STATUS 0x04, RTADDR 0x08, CMD 0x0C, RXDATA 0x10, TXDATA 0x14, IER 0x18, ISR 0x1C (W1C), ERR 0x20 (W1C)

Standards & Compliance

MIL-STD-1553B (Manchester II, 1 Mbps, dual-redundant bus A/B); DO-254/ED-80 airborne electronic hardware design-assurance framing; ISO 26262 ASIL-B SEooC (SPFM 93.75%, LFM 90.00%, PMHF 1.58×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 93.75% · LFM 90.00% · PASS

ISO 26262-5 FMEDA method (transferable evidence for the RTCA DO-254 assurance case) · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	0x04 STATUS 0x08 RTADDR 0x0C CMD 0x10 RXDATA
`0x14`	TXDATA	0x18 IER 0x1C ISR(W1C) 0x20 ERR(W1C) [1]TXDATA_REQ [0]RX_VALID

Getting Started

// Minimal instantiation
mil1553 #(
  .ADDR_W(6)
) u_mil1553 (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in avionics, defense, and space systems built to the ARINC, MIL-STD, and CCSDS standards.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in MIL-STD-1553B Remote Terminal (RT) Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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