AI Inference & Acceleration

NPU Activation Engine — Transformer Post-GEMM Unit

Self-checking fixed-point activation-function engine for transformer/LLM inference pipelines — softmax/LayerNorm/RMSNorm/GELU/SiLU/tanh/ReLU with…

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ASIL-B

target

96.40%

SPFM

91.60%

LFM

Informational

FMEDA

2.2K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

Self-checking fixed-point activation-function engine for transformer/LLM inference pipelines — softmax/LayerNorm/RMSNorm/GELU/SiLU/tanh/ReLU with… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

npu_act is a self-checking activation-function engine for transformer / LLM inference: it computes one of seven per-row functions — softmax, LayerNorm, RMSNorm, GELU, SiLU, tanh, or ReLU — on the INT16 stream leaving a GEMM / attention block, entirely in fixed point (Q16.16 internal, Q8.8 streaming output).

Key Features

Seven activation/normalization modes (CTRL.MODE) in Q16.16 fixed point: softmax, LayerNorm, RMSNorm, GELU, SiLU, tanh, ReLU
Algorithmic (non-LUT) kernels: base-2 exponential decomposition + 3-term Taylor polynomial, 2-step Newton-Raphson reciprocal, 64-iteration restoring square root
ABFT online invariants recomputed on the OUTPUT stream — softmax row-sum == 1.0, LayerNorm zero-mean/unit-variance — flagged as err\_code 3 at near-zero area cost
SECDED-protected line buffer (ecc\_pkg, err\_code 2); config-register even parity across CTRL/ROWLEN/IN_SCALE/EPS/ABFT_TOL (err\_code 1)
Diverse-DMR control FSM (complementary shadow, KEEP\_ATTR) catches a sequencer divergence as err\_code 9
AXI4-Stream slave/master data plane (signed INT16 in, saturating INT16 Q8.8 out) + APB4-lite config/status sidecar — no tensor data ever crosses the config plane
Fully deterministic streaming FSM: bit-exact, replayable output for a given row + configuration, independent of m_axis_tready backpressure timing

Standards & Compliance

ISO 26262 ASIL-B (SEooC: SPFM 96.40%, LFM 91.60%, PMHF 1.59×10⁻⁹/h); pairs with ai_mac / tensor_dma / lm_head (AI subsystem)

Functional Safety

ASIL-B target (SEooC) · SPFM 96.40% · LFM 91.60% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [2:0]=MODE, [3]=EN
`0x04`	ROWLEN	RW [15:0] elements per row (1..MAX_ROW)
`0x08`	IN_SCALE	RW [31:0] Q16.16 input scale (element_real = int16 * IN_SCALE)
`0x0C`	EPS	RW [31:0] Q16.16 variance/denominator epsilon (LayerNorm / RMSNorm)
`0x10`	ABFT_TOL	RW [31:0] Q16.16 invariant tolerance (softmax row-sum / LN moments)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
npu_act #(
 .ADDR_W(6)
) u_npu_act (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in safety-critical edge inference — ADAS, autonomous robotics, and machine vision.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in NPU Activation Engine — Transformer Post-GEMM Unit?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space