Cryptography & Data Integrity

PKA

The PKA IP is a hardware accelerator for the public-key cryptography behind secure boot, firmware authentication,

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ASIL-B

target

98.55%

SPFM

78.61%

LFM

PASS

FMEDA

229K

gates

1.0.0

version

The deliverable

What you’re licensing

The PKA IP is a hardware accelerator for the public-key cryptography behind secure boot, firmware authentication, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

Overview

The PKA IP is a hardware accelerator for the public-key cryptography behind secure boot, firmware authentication, and TLS handshakes — RSA modular exponentiation and NIST P-256/P-384 ECC point operations, built on a single hardware primitive: constant-time Montgomery modular multiplication.

Key Features

Constant-time Montgomery ModMul core — fixed n²+3n+7 cycles for a KEYLEN of n words, spanning RSA-512 through RSA-4096 and ECC P-256/P-384, with ModExp/ECCadd/ECCmul firmware-orchestrated on top of it.
Single APB4 aperture, word-serial register interface (OP_A_IN/OP_B_IN/MOD_IN/EXP_IN with auto-incrementing WORD_OFF) — no separate data plane and no interrupt output; firmware polls STATUS.
Configuration parity on CTRL.OP and KEYLEN → err_code 1.
Per-word parity across every operand/result/Montgomery-intermediate register (A/B/M/E/S/Sm plus mprm_x/m_prime/ui/carry) → err_code 2, the block’s largest fault region at 98.47% measured SPF coverage.
Diverse-DMR FSM lockstep — thermometer-coded primary state vs. a bitwise-NOT one-hot shadow, KEEP_ATTR-protected through synthesis → err_code 9.
Measured ASIL-B metrics from gate-level fault injection: SPFM 98.55%, LFM 78.61%, PMHF 6.26×10⁻⁸/h — PASS.
SWRST is the RTL’s highest-priority action, overriding the FSM even against a simultaneous DONE assertion, for clean fault recovery and operation abort.

Standards & Compliance

ISO 26262 ASIL-B (SEooC); RSA modular exponentiation and NIST FIPS 186-5 ECDSA / SP 800-56A ECDH over P-256 and P-384; constant-time Montgomery modular multiplication (side-channel-resistant core).

Functional Safety

ASIL-B (SEooC) · SPFM 98.55% · LFM 78.61% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=START [1]=SWRST [3:2]=OP WO
`0x04`	STATUS	[0]=BUSY [1]=DONE [2]=ERROR RO
`0x08`	KEYLEN	[7:0] key length in 32-bit words
`0x0C`	reserved
`0x10`	WORD_OFF	[7:0] word-index for next operand write (auto-increments)

…5 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
pka #(
  .ADDR_W(6)
) u_pka (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in PKA?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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