System, Safety & Compute

PLL Guard

pllguard is the clock-integrity safety supervisor for an SoC’s main PLL,

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ASIL-D

target

99.64%

SPFM

100.00%

LFM

PASS

FMEDA

2.0K

gates

1.0.0

version

The deliverable

What you’re licensing

pllguard is the clock-integrity safety supervisor for an SoC’s main PLL, It is delivered as a licensable soft-IP block engineered as an ASIL-D Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

pll_guard is the clock-integrity safety supervisor for an SoC’s main PLL, delivered as synthesizable SystemVerilog soft-IP with an APB4-lite control interface and built-in ISO 26262 (ASIL-D) safety instrumentation.

Key Features

Lock supervision: loss, acquire-watchdog, bounce (P1/P2/P3)
Frequency-in-band via Gray-counter CDC vs [F_MIN,F_MAX] (P4)
lock^frequency cross-check catches “locked-but-wrong” (P5)
Glitch-free safe-clock switchover + sticky safe_state_o actuation (P6)
DMR-protected detection datapath + config parity (gate-FI measurable)

Standards & Compliance

ISO 26262 (ASIL-D), SEooC

Functional Safety

ASIL-D (SEooC) · SPFM 99.64% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN, [1]=FREQ_CHK, [2]=BOUNCE_CHK, [3]=ACQ_CHK
`0x04`	LOCK_TO	RW [31:0] lock-acquire watchdog timeout (clk cycles from enable; 0=off)
`0x08`	F_MIN	RW [15:0] lower band: min pll_clk_i ticks per window
`0x0C`	F_MAX	RW [15:0] upper band: max pll_clk_i ticks per window
`0x10`	WINDOW	RW [15:0] frequency-measure window length (clk cycles)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
pll_guard #(
  .ADDR_W(6)
) u_pll_guard (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in PLL Guard?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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