Serial, Networking & Storage

PSI5 Sensor-Interface Receiver

Single-channel PSI5 (Peripheral Sensor Interface 5) receiver — Manchester decode, parity or 3-bit CRC, sync-pulse generation, ASIL-B.

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ASIL-B

target

93.50%

SPFM

90.00%

LFM

PASS

FMEDA

1.4K

gates

1.1.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

PSI5 Sensor-Interface Receiver routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Single-channel PSI5 (Peripheral Sensor Interface 5) receiver — Manchester decode, parity or 3-bit CRC, sync-pulse generation, ASIL-B. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable PSI5 (Peripheral Sensor Interface 5) receiver delivered as synthesizable SystemVerilog soft-IP. PSI5 is a two-wire, current-loop automotive sensor interface used heavily in airbag, chassis, and powertrain systems: the sensor is powered over the loop and sends Manchester-coded data by modulating loop current.

Key Features

PSI5 Manchester (IEEE) frame decode: 2 start bits + 1–28 configurable data bits (LSB first) + a trailing integrity field, at a programmable bit rate (BITDIV)
Selectable integrity check: single parity bit (even/odd via CTRL.PAR_ODD) or a 3-bit CRC (CTRL.CRC_EN, poly x³+x+1) that catches all 1- and 2-bit errors and 3-bit bursts — a single parity bit misses even-count errors
Programmable psi5_sync pulse output (SYNCPER) drives synchronous-mode sensor time slots, the mechanism a shared-loop multi-sensor bus relies on for time-division access
Fault detection surfaced in ERR/err_code and the interrupt: parity/CRC mismatch, Manchester coding violation (no mid-bit transition), and start-bit error
Complementary-redundant (diverse-DMR) shadow of the decode FSM, independently re-derived every cycle and compared to the live state — a mismatch reports err_code 9
Even-parity protection on the CTRL/BITDIV/CFG configuration registers, reported as err_code 1 into the shared safety_monitor
APB4 slave register interface with maskable frame/error interrupt (psi5_irq); DATA/DATA_HI hold up to 28 received data bits for readback

Standards & Compliance

PSI5 (Peripheral Sensor Interface 5), two-wire current-loop automotive sensor bus; ISO 26262 ASIL-B SEooC, engineering-FMEDA PASS (SPFM 93.50%, LFM 90.00%, PMHF 1.77×10⁻⁹/h, pre-sign-off)

Functional Safety

ASIL-B (SEooC) · SPFM 93.50% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	0x04 STATUS 0x08 BITDIV 0x0C CFG 0x10 DATA (bits [15:0])
`0x14`	DATA_HI	(bits [27:16], upper 12 bits for 17-28 bit configs)
`0x18`	SYNCPER	0x20 IER 0x24 ISR 0x28 ERR

Getting Started

// Minimal instantiation
psi5 #(
 .ADDR_W(6)
) u_psi5 (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in PSI5 Sensor-Interface Receiver?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space