Motor, Power & Sensor Control

Quadrature Encoder Interface (eQEP)

A configurable Quadrature Encoder Interface (QEI / eQEP) delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

100.00%

SPFM

100.00%

LFM

PASS

FMEDA

2.2K

gates

1.0.0

version

The deliverable

What you’re licensing

A configurable Quadrature Encoder Interface (QEI / eQEP) delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable Quadrature Encoder Interface (QEI / eQEP) delivered as synthesizable SystemVerilog soft-IP.

Key Features

A/B quadrature decode — position counter + direction bit
Z-index / STROBE capture for reference marking
Configurable count mode (quadrature, pulse-direction, UP)
32-bit position counter with overflow interrupt
Config-register parity (err_code 1)
DMR lockstep (err_code 9)

Standards & Compliance

JESD86-A incremental encoder interface (generic eQEP pattern)

Functional Safety

ASIL-B (SEooC) · SPFM 100.00% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN [1]=IDX_RST (index pulse zeroes POS) [2]=DIR_INV
`0x04`	STATUS	[0]=DIR (1=up/forward) [1]=IDX_SEEN (sticky) [2]=VEL_REJECT (last reading tossed)
`0x08`	POS	position count (RO) 0x0C MAXCNT modulus; 0 = free-running 2^W
`0x10`	VEL	signed net steps in last window (RO) 0x14 VELDIV window length in clocks
`0x18`	IER	[0]=IDX_IE [1]=WRAP_IE 0x1C ISR [0]=IDX [1]=WRAP (write-1-to-clear)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
qei #(
  .ADDR_W(6)
) u_qei (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in motor drives, power conversion, and sensor front-ends in automotive and industrial systems.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Quadrature Encoder Interface (eQEP)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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