Drone, Robotics & UAV Safety

RC Link Receiver/Decoder

Multi-protocol RC-link decoder (SBUS/CRSF/PPM) for UAV/drone flight control, with hardware failsafe and ASIL-B safety instrumentation.

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ASIL-B

target

93.75%

SPFM

90.00%

LFM

Informational

FMEDA

5.3K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

RC Link Receiver/Decoder routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Multi-protocol RC-link decoder (SBUS/CRSF/PPM) for UAV/drone flight control, with hardware failsafe and ASIL-B safety instrumentation. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

rc_receiver is a multi-protocol RC-link decoder for drone / UAV flight control, delivered as synthesizable SystemVerilog soft-IP on an APB4-lite slave with built-in ASIL-B safety instrumentation.

Key Features

Three protocols, one input: SBUS (inverted UART, 100 kBaud, 8E2, 25-byte frame), CRSF/ELRS (UART, 420 kBaud, CRC8 poly 0xD5), PPM (pulse-width channels + sync gap) — APB-selectable via CTRL.PROTO
16 × 11-bit decoded channels plus failsafe / frame_lost / fresh status, all APB-readable from CHAN0..CHAN15 (0x40-0x7C) and STATUS (0x10)
Staleness watchdog (FRAME_TO, in clk cycles) drives a deterministic hardware failsafe when the link goes silent — err_code 4 — independent of software polling
Per-frame integrity checking — SBUS framing/end-byte + 8E2 parity, CRSF CRC8, PPM pulse-width range — latches err_code 3 and sets frame_lost on any corrupted frame
Config-register even parity over CTRL/BAUDDIV/FRAME_TO/PPM_CFG catches an SEU in the link configuration — err_code 1
KEEP_ATTR complementary-redundant (DMR) shadow of the decode FSM, keyed on an independent next-state cone, catches a fault in the decoder’s own control logic — err_code 9
fi_parity/fi_frame/fi_crc/fi_ppm/fi_stale/fi_dmr fault-inject strobes (also reachable via the FI register) prove every safety mechanism actuates in DFT/fault-injection campaigns

Standards & Compliance

SBUS, CRSF/ELRS, PPM RC-link protocols; ISO 26262 ASIL-B SEooC (SPFM 93.75%, LFM 90.00%, PMHF 6.29×10⁻⁹/h)

Functional Safety

ASIL-B target (SEooC) · SPFM 93.75% · LFM 90.00% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]EN [2:1]PROTO(0=SBUS,1=CRSF,2=PPM) [3]INV(SBUS line invert)
`0x04`	BAUDDIV	[15:0] 16x-oversample divisor = clk/(16*baud)
`0x08`	FRAME_TO[31:0]	staleness watchdog timeout in clk cycles (0 = disabled)
`0x0C`	PPM_CFG	[15:0]=PW_MIN [31:16]=PW_MAX (PPM pulse-width window, clk cycles)
`0x10`	STATUS	RO [0]FAILSAFE [1]FRAME_LOST [2]FRESH [3]ERR_VALID [7:4]ERR_CODE [12:8]CHAN_CNT

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
rc_receiver #(
 .ADDR_W(6)
) u_rc_receiver (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in UAV flight controllers and robotics platforms operating under a functional-safety mandate.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in RC Link Receiver/Decoder?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space