System, Safety & Compute

RISC-V Debug Module (DM)

A synthesizable SystemVerilog implementation of the RISC-V Debug Module (DM) register file, per the RISC-V Debug Specification v1.0.

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ASIL-B

target

93.25%

SPFM

90.00%

LFM

PASS

FMEDA

963

gates

2.7.0

version

The deliverable

What you’re licensing

A synthesizable SystemVerilog implementation of the RISC-V Debug Module (DM) register file, per the RISC-V Debug Specification v1.0. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A synthesizable SystemVerilog implementation of the RISC-V Debug Module (DM) register file, per the RISC-V Debug Specification v1.0.

Key Features

Full RISC-V Debug Spec v1.0 CSR set over one APB4 slave: dmcontrol, dmstatus, hartinfo, abstractcs, command, abstractauto, nextdm, haltsum0, authdata, and the program buffer (progbuf0..N)
Per-hart vectored halt/resume/reset control (dm_haltreq / dm_resumereq / dm_hartreset / dm_halt_on_reset) for up to NUM_HARTS harts, with dmstatus all*/any* aggregation and a haltsum0 halted-bitmask
System Bus Access (SBA): an independent APB master (sb_p*) for 8/16/32-bit debugger reads/writes with autoincrement, decoupled from the hart-control path
Split abstract-command model: cmd_req / cmd_word / cmd_data0 dispatch to an integrator hart-debug executor, with abstractauto.autoexecdata0 streaming for fast GPR/CSR scan
Authentication framework (REQUIRES_AUTH, authdata, auth_grant_i / auth_clear_i) for production debug locking, independent of the dmactive gate
ASIL-B safety overlay: config parity (err_code 1), abstract-command and SBA access-fault protocol errors — bus error/misaligned/oversized (err_code 3) — and dual complementary-DMR lockstep on dmactive and the SBA FSM (err_code 9)
Catalog FMEDA (pre-sign-off engineering numbers): SPFM 93.25%, LFM 90.00%, PMHF 1.22×10⁻⁹/h — PASS against the ASIL-B target, at 2,631 generic cells

Standards & Compliance

RISC-V External Debug Support / RISC-V Debug Specification v1.0 (RISC-V International); AMBA APB4 (register slave + SBA master); ISO 26262 ASIL-B SEooC (SPFM 93.25%, LFM 90.00%, PMHF 1.22×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 93.25% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x10 (0x04)`	data0
`0x40 (0x10)`	dmcontrol
`0x44 (0x11)`	dmstatus	(RO)
`0x48 (0x12)`	hartinfo	(RO, 0)
`0x58 (0x16)`	abstractcs

…2 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
riscv_dm #(
  .ADDR_W(6)
) u_riscv_dm (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in RISC-V Debug Module (DM)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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