Cryptography & Data Integrity

Root-of-Trust / Measured-Boot Controller

Hardware root of trust: an OTP-anchored measured-boot gate that holds a RISC-V core’s first fetch until the boot image authenticates…

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ASIL-B

target

100.00%

SPFM

100.00%

LFM

PASS

FMEDA

4.1K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Root-of-Trust / Measured-Boot Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Hardware root of trust: an OTP-anchored measured-boot gate that holds a RISC-V core’s first fetch until the boot image authenticates… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

Rot — Introduction

What it is

A hardware root-of-trust / measured-boot controller: an APB4-configured FSM that holds a RISC-V core’s instruction fetch (core_fetch_en) LOW until the boot image has been hashed and matched against an OTP-provisioned reference digest, releasing the core only on an authenticated match.

Key Features

Six-state measured-boot FSM (LOCKED → MEASURE → SETTLE → VERIFY → UNLOCKED/FAIL); core_fetch_en asserted iff UNLOCKED, reached only from a matching VERIFY — formally proven, no skip/shortcut path
UNLOCKED and FAIL are sticky terminal states: once authenticated the gate never re-closes, once failed it never un-fails without a full reset — no software bypass of a failed boot decision
Orchestrates rather than computes: drives an external hash-engine handshake (hash_start/base/len → hash_done/digest) normally wired to the catalog’s own sha256 IP
Reference-digest per-word even parity (err_code 1) — a corrupted OTP-loaded anchor cannot silently accept a tampered image
Measured-digest per-word parity (err_code 2) closes the residual single point where a captured-hash bit-flip could spuriously match the reference
Verify-decision spatial DMR (err_code 9, dual KEEP_ATTR cones) plus a measure-FSM duplicate-DMR shadow (err_code 3) — a single-point fault cannot silently force a false authentication
Catalog FMEDA: 4101 cells, SPFM 100.00%, LFM 100.00%, PMHF 0/h — PASS against the ASIL-B target with full margin

Standards & Compliance

AMBA APB4 (ARM IHI 0024); orchestrates the catalog’s sha256 hash engine and OTP fuse macro; ISO 26262 ASIL-B SEooC (SPFM 100.00%, LFM 100.00%, PMHF 0/h)

Functional Safety

ASIL-B (SEooC) · SPFM 100.00% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00..0x1C`	REF[0..7]	RW reference digest words (from OTP at provisioning)
`0x20`	BASE	RW boot-image base address (passed to the hash engine)
`0x24`	LEN	RW boot-image length
`0x28`	CTRL	RW bit0 = start (self-clearing)
`0x2C`	STATUS	RO [0]=measuring [1]=fetch_en(authenticated) [2]=fail

Getting Started

// Minimal instantiation
rot #(
 .ADDR_W(6)
) u_rot (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Root-of-Trust / Measured-Boot Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space