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Display, Imaging & Multimedia

safe_video — Video Pipeline Integrity Monitor

Observe-only camera-to-cluster video watchdog that proves a frame is live, unfrozen, and content-intact wherever it taps the chain…

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ASIL-B
target
94.00%
SPFM
89.49%
LFM
Informational
FMEDA
3.0K
gates
1.0.0
version
Interfaces at a glance

Block diagram

safe_video18 portsapb_slave8 signalssofeofpix_validpix_datasrc_seqclkrst_nsafety / statuserr_clear · err_valid · err_code
Place-and-route snapshot

Physical implementation

safe_video — Video Pipeline Integrity Monitor routed place-and-route layout on the Nangate45 PDK
A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.
The deliverable

What you’re licensing

Observe-only camera-to-cluster video watchdog that proves a frame is live, unfrozen, and content-intact wherever it taps the chain… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL
Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.
Per-IP FMEDA report
SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.
Safety manual
Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.
IP-XACT + integration docs
A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.
Self-checking testbench
A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

safe_video is a safety-video pipeline monitor — synthesizable SystemVerilog soft-IP with an APB4-lite control interface and built-in ISO 26262 (ASIL-B/D) safety instrumentation that proves a video stream is live, unfrozen, and content-intact anywhere it sits in the chain, from camera ingest all the way to the final frames driven onto an instrument-cluster display.

Key Features

Standards & Compliance

AMBA APB4 (ARM IHI 0024); ISO 26262 ASIL-B SEooC (SPFM 94.00%, LFM 89.49%, PMHF 3.63×10⁻⁹/h); ecc_pkg SECDED storage protection

Functional Safety

ASIL-B target (SEooC) · SPFM 94.00% · LFM 89.49% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

OffsetRegisterDescription
0x00CTRLRW [0]=EN, [1]=SIG_CHK, [2]=SEQ_CHK, [3]=TO_EN
0x04EXP_SIGRW [31:0] expected per-frame signature (M1, checked when SIG_CHK)
0x08EXP_PIXRW [31:0] expected pixels per frame (M6 geometry; 0=disabled)
0x0CTHRESHRW [7:0]=BLANK_LO, [15:8]=BLANK_HI, [23:16]=FREEZE_N
0x10FRAME_TORW [31:0] frame timeout in clock cycles (M5; 0=disabled)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
safe_video #(
 .ADDR_W(6)
) u_safe_video (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in instrument clusters, camera pipelines, and safety-monitored display paths.

The case

Why license it, not build it

Skip 12–18 months
The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.
One vendor, one safety story
Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.
Verified, not vapor
The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in safe_video — Video Pipeline Integrity Monitor?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space