Cryptography & Data Integrity

SecOC AES-128 CMAC Engine

AUTOSAR SecOC hardware offload — AES-128 CMAC + freshness anti-replay for authenticated CAN / CAN-FD / automotive-Ethernet PDUs, ASIL-B.

Request this IP →Browse the catalog

ASIL-B

target

98.73%

SPFM

100.00%

LFM

Informational

FMEDA

18.6K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

SecOC AES-128 CMAC Engine routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

AUTOSAR SecOC hardware offload — AES-128 CMAC + freshness anti-replay for authenticated CAN / CAN-FD / automotive-Ethernet PDUs, ASIL-B. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

secoc is an AUTOSAR SecOC (Secure Onboard Communication) MAC engine, delivered as synthesizable SystemVerilog soft-IP with an APB4-lite control interface and built-in ISO 26262 (ASIL-B) safety instrumentation.

Key Features

AES-128 CMAC (NIST SP 800-38B / RFC 4493) over { data-id || payload || freshness }, with a configurable 24/28/32-bit truncated MAC and a multi-block PDU buffer (BUF_BLOCKS parametric depth)
Generate (TX) and verify (RX) modes selected per run via CTRL.VERIFY — deploy one instance per direction with matching KEY/DATA_ID/MACLEN
Freshness anti-replay: accepted only if strictly increasing and within a configurable forward-jump window; the anchor advances only on a fully-accepted PDU, rejecting stale or replayed traffic
Config-register even parity over KEY/DATA_ID/MACLEN/FRESH_WIN -> err_code 1; a corrupted key or window is caught before it can silently pass or reject traffic
MAC-verify FAIL or freshness/anti-replay violation -> err_code 3, so a forged, tampered, or replayed message is a DETECTED fault, never a silent accept
KEEP_ATTR dual-rail DMR of the CMAC control FSM -> err_code 9, plus a verify-watchdog timeout -> err_code 4 and fi_* DFT taps (including fi_mac_flip) that prove each detector fires
APB4-lite config + sticky STATUS telemetry and a DONE interrupt; catalog FMEDA SPFM 98.73%, LFM 100.00%, PMHF 4.44×10⁻⁹/h, PASS ASIL-B

Standards & Compliance

AUTOSAR SecOC; AES-128 CMAC (NIST SP 800-38B / RFC 4493); APB4-lite config slave; ISO 26262 ASIL-B SEooC (SPFM 98.73%, LFM 100.00%, PMHF 4.44×10⁻⁹/h); ISO 21434 cybersecurity (message authenticity/freshness)

Functional Safety

ASIL-B target (SEooC) · SPFM 98.73% · LFM 100.00% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=START (kick the CMAC engine) [1]=VERIFY (1=RX/verify, 0=TX/generate) [2]=LAST_K2 (final block was zero-padded ->…
`0x04`	STATUS	RO [0]=BUSY [1]=DONE [2]=MAC_OK (last verify matched) [3]=FRESH_OK [4]=MAC_FAIL (last verify mismatch) [5]=REPLAY_FAI…
`0x08..0x14`	KEY0..3	128-bit CMAC key (KEY0=MSW)
`0x18`	DATA_ID	16-bit SecOC data identifier (low half-word used)
`0x1C`	MACLEN	truncated MAC length in bits (24 / 28 / 32 supported; clamped 1..32)

…7 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
secoc #(
 .ADDR_W(6)
) u_secoc (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SecOC AES-128 CMAC Engine?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space