Serial, Networking & Storage

SAE J2716 SENT Sensor Receiver

A configurable SAE J2716 SENT receiver, delivered as synthesizable SystemVerilog soft-IP: it recovers a sensor’s single-wire,

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ASIL-B

target

93.50%

SPFM

90.00%

LFM

PASS

FMEDA

2.9K

gates

1.0.0

version

The deliverable

What you’re licensing

A configurable SAE J2716 SENT receiver, delivered as synthesizable SystemVerilog soft-IP: it recovers a sensor’s single-wire, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable SAE J2716 SENT receiver, delivered as synthesizable SystemVerilog soft-IP: it recovers a sensor’s single-wire, tick-encoded nibble stream, decodes and CRC-checks each frame, and presents the result over an APB4 register interface with built-in ASIL B safety instrumentation.

Key Features

SAE J2716 frame decode: 56-tick sync/calibration pulse, status nibble, 1–6 data nibbles, and a CRC nibble, all measured as falling-edge-to-falling-edge tick counts
Drift-tolerant tick calibration: the true tick period is re-measured from every frame’s sync pulse (SYNCPER diagnostic readback), so TICKDIV only needs to be within ±25% of nominal
CRC-4 (seed 5, table lookup + augmentation round) computed over the data nibbles every frame; STATUS.CRC_OK always reflects it, and CTRL.CRC_CHK_EN routes a mismatch into ERR.CRC_ERR / err_code 3
Even-parity protection on every configuration register — CTRL, TICKDIV, CFG, and the SPC_CTRL (Short PWM Code) trigger-window register — reported as err_code 1
Diverse-DMR complementary shadow of the frame-decode FSM (SEEK/NIBWAIT/DIV/DONE), independently re-derived every cycle and compared to the live state — a mismatch reports err_code 9
Optional SPC (Short PWM Code) trigger gating: a configurable dominant-pulse-width window (SPC_TRIG_LO/HI) arms frame capture only after a qualifying trigger pulse
Maskable frame-complete / error interrupt (sent_irq); no internal frame-arrival timeout — ERR.SYNC_ERR is reserved but never asserted, so the host must apply its own watchdog for a stalled or disconnected sensor

Standards & Compliance

SAE J2716 (SENT); ISO 26262 ASIL-B SEooC, engineering-FMEDA PASS (SPFM 93.50%, LFM 90.00%, PMHF 3.60×10⁻⁹/h, pre-sign-off)

Functional Safety

ASIL-B (SEooC) · SPFM 93.50% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	0x04 STATUS 0x08 TICKDIV 0x0C CFG 0x10 DATA
`0x14`	FRAME	0x18 SYNCPER 0x20 IER 0x24 ISR 0x28 ERR 0x2C SPC_CTRL

Getting Started

// Minimal instantiation
sent #(
  .ADDR_W(6)
) u_sent (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SAE J2716 SENT Sensor Receiver?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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