Cryptography & Data Integrity

SHA-256/SHA-512 Hash Accelerator

A dual-mode FIPS 180-4 hash accelerator — SHA-256 (default, 64 rounds) and SHA-512 (80 rounds),

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ASIL-B

target

95.00%

SPFM

90.00%

LFM

PASS

FMEDA

8.5K

gates

1.0.0

version

The deliverable

What you’re licensing

A dual-mode FIPS 180-4 hash accelerator — SHA-256 (default, 64 rounds) and SHA-512 (80 rounds), It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A dual-mode FIPS 180-4 hash accelerator — SHA-256 (default, 64 rounds) and SHA-512 (80 rounds), selected by a MODE register — delivered as synthesizable SystemVerilog soft-IP with an APB4 slave interface.

Key Features

Dual-mode FIPS 180-4 engine: SHA-256 (64 rounds, 512-bit block → 256-bit digest) or SHA-512 (80 rounds, 1024-bit block → 512-bit digest), selected by MODE (0x70[0])
On-the-fly message schedule via a 16-word sliding window — no 64-word schedule buffer; one round per clock plus a finalize cycle
CTRL.INIT reloads the FIPS initial hash values; repeated CTRL.START calls chain multi-block messages onto the running hash
ASIL B complementary-shadow DMR on the persistent hash state (H_q vs ~Hc_q) → err_code 9
ASIL B CTRL.SELFTEST known-answer self-test of the live compression datapath against the SHA-256(“”) golden vector → err_code 2
Mandatory system-level digest comparison covers the compression datapath itself — the SHA-256 avalanche property turns any internal fault into roughly half the digest bits flipping
APB4 slave interface (ADDR_W=7 default, ADDR_W=8 for the full SHA-512 DIGEST_HI0..7 readback); maskable DONE interrupt (sha_irq); 8,455 generic cells, logic depth 2,087

Standards & Compliance

FIPS 180-4 (SHA-256/SHA-512), NIST SP 800-107 (hash security), NIST CAVS-validated test vectors. ASIL B — ISO 26262-5

Functional Safety

ASIL-B (SEooC) · SPFM 95.00% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=INIT (W1: H <- FIPS IVs) [1]=START (W1: compress the loaded block)
`0x04`	STATUS	RO [0]=BUSY [1]=DONE
`0x08..0x44`	MSG0..MSG15	(16×32-bit, SHA-256 block OR SHA-512 block words 0..15)
`0x48..0x64`	DIGEST0..DIGEST7	(RO H[0..7] low 32 bits, valid for both modes)
`0x68`	IER	[0]=DONE_IE 0x6C ISR RW1C [0]=DONE

…2 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
sha256 #(
  .ADDR_W(6)
) u_sha256 (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SHA-256/SHA-512 Hash Accelerator?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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