Avionics, Space & Mil-Std Networking

SpaceWire RMAP Target/Initiator Engine

spacewirermap is a SpaceWire RMAP (Remote Memory Access Protocol, ECSS-E-ST-50-52C) target and initiator engine: it lets one SpaceWire node read,

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ASIL-B

target

91.40%

SPFM

88.52%

LFM

PASS

FMEDA

4.6K

gates

1.0.0

version

The deliverable

What you’re licensing

spacewirermap is a SpaceWire RMAP (Remote Memory Access Protocol, ECSS-E-ST-50-52C) target and initiator engine: it lets one SpaceWire node read, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

spacewire_rmap is a SpaceWire RMAP (Remote Memory Access Protocol, ECSS-E-ST-50-52C) target and initiator engine: it lets one SpaceWire node read, write, or read-modify-write the memory or register space of another node without running software on the remote end.

Key Features

RMAP target: full command-header decode (logical address / protocol-id / instruction / key / transaction-id / 32-bit address / 24-bit data-length / header-CRC), a req/gnt/rvalid memory bus tolerant of any read latency, and a status-coded reply (OK / key-error 0x03 / invalid-instruction 0x02 / header-CRC 0x07 / data-CRC 0x08) with read data + data-CRC
RMAP initiator: assembles a read or write command with a correct header-CRC (and, for writes, data-CRC) from configured LADDR/KEY/MEMBASE, and parses the inbound reply’s status byte into INI_STAT
One shared RMAP CRC-8 (polynomial 0xE7, ECSS-E-ST-50-52C) generate+check byte step accumulates the header-CRC and data-CRC identically on both the target and the initiator
Authorize-then-execute: a destination-key mismatch, header-CRC or data-CRC fault, or invalid instruction rejects the command with an error reply before the memory bus is touched → err_code 3
Bounded transaction-timeout watchdog on the memory-access phase (fixed at 2¹⁶−1 cycles) → err_code 4, catching a hung memory bridge or a reply that never completes
Even-parity protection on the LADDR/KEY/MEMBASE/CTRL config registers → err_code 1; KEEP_ATTR complementary-DMR lockstep on both the command and reply FSMs → err_code 9, all into one safety_monitor with fi_par/fi_crc/fi_timeout/fi_dmr DFT-inject proof points
v0.1 protocol subset (documented AoU, not silent): reply-address-field length 0 / flat addressing only, address always auto-increments (non-incrementing commands not honored), and verify-before-write (RMW compare) is a firmware obligation

Standards & Compliance

SpaceWire RMAP ECSS-E-ST-50-52C target + initiator (external SpaceWire link, ECSS-E-ST-50-12C, via the catalog spacewire codec); ISO 26262 ASIL-B SEooC (SPFM 91.40%, LFM 88.52%, PMHF 7.45×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.40% · LFM 88.52% · PASS

ISO 26262-5 FMEDA method (transferable evidence for the ECSS-Q-ST-60 / radiation case) · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	0x04 STATUS 0x08 LADDR 0x0C KEY 0x10 MEMBASE
`0x14`	INI_CMD	0x18 INI_DAT 0x1C IER 0x20 ISR(W1C) 0x24 ERR(W1C) 0x28 INI_STAT [5]ini_busy [6]ini_done [10:7]last_status[3…

Getting Started

// Minimal instantiation
spacewire_rmap #(
  .ADDR_W(6)
) u_spacewire_rmap (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in avionics, defense, and space systems built to the ARINC, MIL-STD, and CCSDS standards.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SpaceWire RMAP Target/Initiator Engine?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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