Avionics, Space & Mil-Std Networking

SpaceWire-D Deterministic-TDMA Scheduler

Time-slotted deterministic scheduling above SpaceWire — virtual buses, a parity-protected schedule table, and an ASIL-B safety overlay.

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ASIL-B

target

95.60%

SPFM

92.35%

LFM

Informational

FMEDA

3.2K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

SpaceWire-D Deterministic-TDMA Scheduler routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Time-slotted deterministic scheduling above SpaceWire — virtual buses, a parity-protected schedule table, and an ASIL-B safety overlay. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

spw_d is a SpaceWire-D deterministic-TDMA scheduling layer delivered as synthesizable SystemVerilog soft-IP, with a rad-tolerant / ASIL-B safety overlay (fault latch, schedule-table + config parity, slot-counter & FSM DMR shadow, slot-overrun / schedule-conflict / time-sync watchdogs).

Key Features

Time-code-driven epoch scheduling: a free-running slot counter (0..63, programmable EPOCH_LEN) advances on each SpaceWire time-code (tc_tick/tc_value), phase-locked to the network’s shared time base
Parity-protected per-slot schedule table (SLOT_SEL/SLOT_DAT, {alloc,vbus[3:0]} entries) — the network-wide virtual-bus timing plan, loaded over APB4 before CTRL.EN; an SEU in a stored entry -> err_code 1 and blocks any grant
Deterministic transaction gating: tx_grant/tx_active issue-enable only when the current slot is ALLOC’d to this node and the requested vbus matches the schedule — a foreign-slot request is silently refused, never faulted
SLOT-OVERRUN detection: a granted transaction still active at the slot boundary is aborted and flagged -> err_code 3 — the core SpaceWire-D real-time guarantee
SCHEDULE-CONFLICT detection: a time-code that does not advance the slot counter by exactly one (skipped/duplicated/garbled tick) -> err_code 3
EPOCH-SYNC TIMEOUT watchdog: no time-code within EPOCH_TO clk cycles once running -> err_code 4 (lost network time sync)
KEEP_ATTR complementary-DMR shadow on the slot counter and schedule FSM -> err_code 9, plus config-register parity and a shared safety_monitor self-check (err_code F); fi_* DFT inputs prove every mechanism at gate level

Standards & Compliance

ECSS-E-ST-50-12C SpaceWire-D determinism profile; ISO 26262 ASIL-B SEooC (SPFM 95.60%, LFM 92.35%, PMHF 2.78×10⁻⁹/h — informational, Technology Preview)

Functional Safety

ASIL-B target (SEooC) · SPFM 95.60% · LFM 92.35% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262-5 FMEDA method (transferable evidence for the ECSS-Q-ST-60 / radiation case) · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	0x04 STATUS 0x08 EPOCH_CFG 0x0C SLOT_SEL 0x10 SLOT_DAT
`0x14`	TXREQ	0x18 IER 0x1C ISR(W1C) 0x20 ERR(W1C) [9]overrun [10]conflict [11]sync_to [14:12]sched_state

Getting Started

// Minimal instantiation
spw_d #(
 .ADDR_W(6)
) u_spw_d (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in avionics, defense, and space systems built to the ARINC, MIL-STD, and CCSDS standards.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SpaceWire-D Deterministic-TDMA Scheduler?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space