Tensor-Layout-Aware DMA Engine (im2col/Tiling)

What it is

tensor_dma is a tensor-layout-aware DMA engine (#A-3): a single-descriptor, strided N-D address generator that reshapes a 1-D feature-map buffer into the overlapping im2col windows a convolution consumes, moving the data entirely in hardware from the axi_tcm scratchpad to the ai_mac tile grid.

Key Features

• Single register-resident descriptor (BASE/IN_LEN/KW/STRIDE/QUANT/CTRL over APB4-lite) drives a 2-D affine address generator addr(col,tap) = BASE + col*STRIDE + tap — no in-memory descriptor ring; NCOLS = (IN_LEN-KW)/STRIDE+1 computed in hardware and readable live before START
• AXI4 burst-read master (INCR, arlen=KW-1, 4-byte beats) pulls one KW-beat window per column from the axi_tcm scratchpad into a MAXLEN-deep SECDED line buffer (fifo_ecc); an uncorrectable double-bit error raises err_code 2
• AXI4-Stream master output (axi4s_bridge convention): tdata/tkeep carry the quantized INT8 operand, tuser = column index for grid broadcast/routing, tlast frames each im2col window
• On-the-fly INT8 quant/dequant: q = sat8((x-ZP)*SCALE>>SHIFT), with QEN=0 raw passthrough; verified bit-exact against a software im2col+quant golden for multiple tile shapes/strides
• Two-layer diverse-DMR on the address generator — a complementary-shadow FSM state plus an independent shadow of the address/counter datapath itself (col/tap/win_base/ncols, hence m_axi_araddr) — both drive err_code 9, so a corrupted read address can no longer reach the bus undetected
• Even-parity shadow over the full config-register set (BASE/IN_LEN/KW/STRIDE/QUANT/CTRL) checked every cycle -> err_code 1; AXI read DECERR/SLVERR sampled on accepted beats -> err_code 7/8
• fi_data_xor/fi_chk_xor/fi_agen_dmr/fi_addr_dmr DFT inject ports (tied 0 in mission mode) exercise every mechanism directly; single clock domain, no CDC in the RTL

Standards & Compliance

AMBA AXI4 read master / AXI4-Stream master (axi4s_bridge convention); APB4-lite config slave; ISO 26262 ASIL-B SEooC (SPFM 96.49%, LFM 100.00%, PMHF 5.37×10⁻⁹/h)

Functional Safety

ASIL-B target (SEooC) · SPFM 96.49% · LFM 100.00% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
tensor_dma #(
 .ADDR_W(6)
) u_tensor_dma (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.