The deliverable
What you’re licensing
tlctochi lets a TileLink-C cache master attach to an AMBA 5 CHI coherent interconnect as a fully-coherent Request Node (RN-F). It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:
Synthesizable RTL
Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.
Per-IP FMEDA report
SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.
Safety manual
Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.
IP-XACT + integration docs
A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.
Self-checking testbench
A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.
What it is
tl_c_to_chi lets a TileLink-C cache master attach to an AMBA 5 CHI coherent interconnect as a fully-coherent Request Node (RN-F).
Key Features
- Forward path: Acquire (NtoB/NtoT/BtoT) → CHI ReadShared/ReadUnique → CompData → GrantData; voluntary Release/ReleaseData → WriteBackFull + CBWrData → synthesised ReleaseAck
- Snoop path: CHI SnpShared/SnpUnique → TL-C Probe (toB/toN); the master’s ProbeAck/ProbeAckData → CHI SnpResp/SnpRespData, forwarding dirty data back into the directory
- Single clock domain, no internal CDC — verified against the RTL (one clk port; every CHI rx/tx port is same-clock synchronous); an integrator-supplied external CDC is required for a different-frequency CHI link
- Composable: tl_c_to_chi_multi packs N single-master bridges (distinct SRCID) around one CHI Home Node for a coherent TL-C cluster with no added coherence logic — it emerges from the HN’s directory
- tl_c_mem_to_chi adapts the catalog’s tl_c_xbar backing-store port to a CHI RN-F, so the real coherence-manager RTL sources/sinks its line data over CHI instead of local SRAM
- ASIL-B safety: config/control parity (err_code 1), 256-bit line-data-buffer parity (err_code 2), CHI/TL-C opcode-legality check (err_code 3), outstanding-transaction watchdog (err_code 4, default 512 cycles), diverse-DMR complementary-FSM lockstep on both engines (err_code 9)
- Verified against the in-house OSS CHI directory Home-Node BFM: 11/11 single-bridge tests, 10/10 two-master cluster tests, 4/4 real-tl_c_xbar-over-CHI composition tests — SPFM 91.05%, LFM 89.34%, PMHF 5.87×10⁻⁹/h (PASS)
Standards & Compliance
TileLink-C v0.3 (A–E channels) ↔︎ AMBA 5 CHI IHI 0050 (RN-F); ISO 26262 ASIL-B SEooC (SPFM 91.05%, LFM 89.34%, PMHF 5.87×10⁻⁹/h)
Functional Safety
ASIL-B (SEooC) · SPFM 91.05% · LFM 89.34% · PASS
ISO 26262:2018 · FMEDA available · Safety Manual included
Register Map
See datasheet for full register reference.
Getting Started
// Minimal instantiation
tl_c_to_chi #(
.ADDR_W(6)
) u_tl_c_to_chi (
.clk (clk),
.rst_n (rst_n),
// APB4
.p_paddr (paddr),
.p_psel (psel),
.p_penable (penable),
.p_pwrite (pwrite),
.p_pwdata (pwdata),
.p_prdata (prdata),
.p_pready (pready),
// Safety
.err_clear (1'b0),
.err_valid (err_valid),
.err_code (err_code)
);
Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.
Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.