Bus Bridges & Interconnect

TileLink-UH-to-AXI4 Bridge

Full TileLink-UH slave → AXI4 master bridge (INCR bursts, multi-outstanding, AMO ALU), ASIL-B/D via ID/address parity, full-word SECDED…

Request this IP →Browse the catalog

ASIL-B

target

91.75%

SPFM

89.14%

LFM

PASS

FMEDA

7.1K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

TileLink-UH-to-AXI4 Bridge routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Full TileLink-UH slave → AXI4 master bridge (INCR bursts, multi-outstanding, AMO ALU), ASIL-B/D via ID/address parity, full-word SECDED… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A TileLink-UH-to-AXI4 protocol bridge: it terminates a TL-UH slave port and drives a full AXI4 master (AR/R/AW/W/B) through a per-slot FSM, so a TL-UH-native RISC-V core or fabric can reach any standard AXI4 slave or interconnect.

Key Features

Full TL-UH ↔︎ AXI4 opcode mapping: TL_GET→AR/R, TL_PUT_FULL/TL_PUT_PARTIAL→AW/W/B, TL_INTENT→HintAck, TL_ARITH/TL_LOGIC→native read-modify-write AMO ALU
Per-slot burst_splitter maps tl_a_size into INCR ARLEN/AWLEN bursts honoring the AXI4 256-beat / 4 KB rules; splitter address/beat-count parity → err_code 2
Up to OUTSTANDING concurrent FSM slots (12 states each) with ID-routed axi_rid/axi_bid return match; a routing mismatch raises protocol err_code 3
Single write-channel lock serializes AW/W ownership across slots (AXI4 W carries no ID) while reads stay fully concurrent
True 64-bit full-word SECDED (ecc_pkg) on write- and read-data beat buffers: single-bit auto-correct, double-bit detect → err_code 2
AXI4 SLVERR/DECERR captured and mapped to TL-D denied/corrupt plus err_code 8/7; per-slot timeout_monitor (TIMEOUT_CYCLES, default 256) synthesizes a denied response and err_code 4 for a hung subordinate
ASIL-D-grade complementary-redundant FSM lockstep: independently duplicated arbiters recompute each slot’s next state from a shadow copy → err_code 9; single clock domain (clk/rst_n), no internal CDC

Standards & Compliance

TileLink-UH (slave, A/D channels); AMBA AXI4 (master, AR/R/AW/W/B, INCR bursts); ISO 26262 ASIL-B SEooC (SPFM 91.75%, LFM 89.14%, PMHF 1.10×10⁻⁸/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.75% · LFM 89.14% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
tl_uh_to_axi4 #(
 .ADDR_W(6)
) u_tl_uh_to_axi4 (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in heterogeneous SoCs that mix AMBA and TileLink IP and need clean, verified protocol and clock-domain crossings.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in TileLink-UH-to-AXI4 Bridge?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space