Serial, Networking & Storage

NS16550A-Compatible UART

Drop-in 16550 UART core — APB4, SECDED FIFOs, diverse-DMR lockstep, ASIL-B.

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ASIL-B

target

97.22%

SPFM

99.00%

LFM

PASS

FMEDA

2.7K

gates

1.5.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

NS16550A-Compatible UART routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Drop-in 16550 UART core — APB4, SECDED FIFOs, diverse-DMR lockstep, ASIL-B. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A NS16550A-register-compatible UART soft-IP with an APB4 slave interface, safety- instrumented for ASIL-B deployment.

Key Features

NS16550A-compatible register map (0x00–0x1C) — unmodified Linux 8250/16550, U-Boot, and bare-metal HAL drivers run as-is
Vendor ERRCNT (0x20): saturating 8-bit parity/framing/overrun counters, write-any-to-clear — diagnostic telemetry no standard 16550 provides
16×-oversampling baud generator, 5–8 data bits, odd/even/mark/space parity, 1–2 stop bits; configurable TX/RX FIFO depth (4–64, default 16)
TX and RX FIFOs SECDED-protected (fifo_ecc): single-bit upsets corrected transparently, double-bit upsets → err_code 2
Diverse-DMR independent lockstep shadow on both the TX and RX serial engines — a divergence → err_code 9
Even-parity protection on baud divisor / LCR / IER config registers → err_code 1; RX parity/framing/overrun aggregate → err_code 3
2-FF metastability synchronizer on uart_rx (no external synchronizer needed); no RTS/CTS hardware flow control — size FIFO_DEPTH against host drain latency

Standards & Compliance

NS16550A register-compatible UART; ISO 26262 ASIL-B SEooC

Functional Safety

ASIL-B (SEooC) · SPFM 97.22% · LFM 99.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	DLAB=0:	RBR (read) / THR (write); DLAB=1: DLL
`0x04`	DLAB=0:	IER; DLAB=1: DLH
`0x08`	IIR	(read) / FCR (write)
`0x0C`	LCR	[7]=DLAB [6]=BC [5]=SP [4]=EPS [3]=PEN [2]=STB [1:0]=WLS
`0x10`	MCR	(not implemented, reads 0)

…4 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
uart #(
 .ADDR_W(6)
) u_uart (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in NS16550A-Compatible UART?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space