Serial, Networking & Storage

USB 2.0 Full-Speed Device Controller

A USB 2.0 Full-Speed (12 Mbps) device controller delivered as synthesizable SystemVerilog soft-IP,

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ASIL-B

target

91.85%

SPFM

91.81%

LFM

PASS

FMEDA

3.2K

gates

0.1.0

version

The deliverable

What you’re licensing

A USB 2.0 Full-Speed (12 Mbps) device controller delivered as synthesizable SystemVerilog soft-IP, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A USB 2.0 Full-Speed (12 Mbps) device controller delivered as synthesizable SystemVerilog soft-IP, presenting an APB4 register interface to the host SoC CPU and a ULPI (UTMI+ Low Pin Interface) link to an external USB2 PHY chip.

Key Features

ULPI 1.1 link to an external USB2 PHY (USB3343/USB3300/TUSB1210/ISP1704A) — single clock domain, no internal CDC; the PHY owns host-side clock/data recovery
SIE decodes SETUP/OUT/IN/SOF token PIDs and routes DATA0/DATA1 payloads to the addressed endpoint by device address + endpoint number
EP0 control (TX+RX) plus configurable bulk-or-interrupt EP1/EP2, each a 64-byte usb2_fifo64 with byte-SECDED storage + complementary-DMR pointers (err_code 2 on an uncorrectable fault)
Even-parity protection on every critical config register (CTRL, INTR_EN, DEV_ADDR, EP0_CTRL, EP1_CTRL, EP2_CTRL) — err_code 1
Diverse-DMR lockstep shadow on the ULPI and SIE FSMs — err_code 9
Saturating protocol-error counter + STATUS.FRAME_ERR on a short/unrecognized token PID — err_code 3
v0.1 Technology Preview: CRC5/CRC16 check-and-generate and ACK/NAK/STALL handshake TX are not yet wired into the datapath (v1.0 roadmap) — informational ASIL-B FMEDA: SPFM 91.85%, LFM 91.81%, PMHF 5.11×10⁻⁹/h

Standards & Compliance

USB 2.0 (Full-Speed), UTMI+ Low Pin Interface (ULPI) 1.1; ISO 26262 ASIL-B SEooC (informational FMEDA — SPFM 91.85%, LFM 91.81%, PMHF 5.11×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.85% · LFM 91.81% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN [1]=SPD [2]=PULLUP [3]=RESET
`0x04`	STATUS	RO [0]=CONN [1]=SUSP [2]=RST_DET [3]=HS_MODE [4]=FRAME_ERR
`0x08`	INTR	W1C [9:0]
`0x0C`	INTR_EN	RW same bits
`0x10`	DEV_ADDR	RW [6:0]

…11 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
usb2_dev #(
  .ADDR_W(6)
) u_usb2_dev (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in USB 2.0 Full-Speed Device Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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