Display, Imaging & Multimedia

Baseline JPEG Video Encoder

videoenc is a baseline (motion-)JPEG luminance image ENCODER for drone payload video (DRONE-8),

Request this IP →Browse the catalog

ASIL-B

target

91.90%

SPFM

87.89%

LFM

PASS

FMEDA

9.2K

gates

1.0.0

version

The deliverable

What you’re licensing

videoenc is a baseline (motion-)JPEG luminance image ENCODER for drone payload video (DRONE-8), It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

video_enc is a baseline (motion-)JPEG luminance image ENCODER for drone payload video (#DRONE-8), delivered as synthesizable SystemVerilog soft-IP with an APB4-lite control interface and built-in ISO 26262 safety instrumentation.

Key Features

Fixed-point 2-D DCT → quantize → Huffman entropy coder
JFIF / SOI..EOI marker framing for decodable .jpg output
Pipeline plausibility + encode-timeout watchdog (err_code 3 / 4)
Config parity + encode-FSM / block-counter diverse-DMR (err_code 1 / 9)
ASIL-B FMEDA — SPFM 91.90% PASS

Standards & Compliance

ITU-T T.81 (baseline JPEG), ISO 26262 (ASIL-B SEooC)

Functional Safety

ASIL-B (SEooC) · SPFM 91.90% · LFM 87.89% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0xFF`	byte-stuffing.	The IP also emits the JFIF/SOI/DQT/DHT/SOF0/SOS marker framing so a -> protocol_in (err_code 3) -> lockstep_in…
`0x00`	CTRL	[0]=ENABLE [1]=START(self-clear, latches block & runs encode) [2]=FRAME_BEGIN(self-clear: emit SOI..SOS header befor…
`0x04`	QUALITY	[7:0]=quality scalar 1..100 (JPEG IJG scale; 50=standard table)
`0x08`	PIXIN	[31:0]=4 packed pixels {p3,p2,p1,p0}; write 16 words = one 8×8 block (raster)
`0x0C`	STATUS	RO [0]=BUSY [1]=DONE(block) [2]=OVF(output overflow) [3]=HDR_RDY

…6 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
video_enc #(
  .ADDR_W(6)
) u_video_enc (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in instrument clusters, camera pipelines, and safety-monitored display paths.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Baseline JPEG Video Encoder?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · sales@circuit-design.space