Timers, Clocks & I/O

Watchdog Timer (WDT)

APB4 watchdog that turns program-flow liveness into a hardware proof obligation, with staged reset escalation and ASIL-B diagnostics.

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ASIL-B

target

99.30%

SPFM

100.00%

LFM

PASS

FMEDA

1.0K

gates

1.10.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Watchdog Timer (WDT) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

APB4 watchdog that turns program-flow liveness into a hardware proof obligation, with staged reset escalation and ASIL-B diagnostics. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable-width APB4 watchdog timer (16 b default, up to 32 b) delivered as synthesizable SystemVerilog soft-IP.

Key Features

Configurable-width down-counter (TIMER_W, default 16 b, up to 32 b) with a LOAD reload register for flexible timeout periods — one decrement per clock, no internal prescaler
Magic-key service/lock: write 0xA5 to KR to kick (reload + clear WDIF), write 0xCC to freeze CR/LOAD/WINDOW until the next reset
Windowed-kick enforcement (CR.WWEN): a kick while cnt_q > WINDOW is a fault (wdt_win pulse + WDIF), not a valid service — catches early/runaway control flow, not just hangs
Two-stage reset escalation: CR.WIE raises a maskable wdt_irq on first timeout (recoverable); CR.WDE gates the one-cycle wdt_rst hard-reset pulse as the last-resort path
ASIL-B diagnostics: even-parity on CR/LOAD/WINDOW → err_code 1; independent-DMR counter shadow + complementary-shadow DMR of the timeout/window flag and pulse flops → err_code 9
Dedicated hardware outputs (wdt_rst/wdt_win/wdt_irq) wired point-to-point to the reset/interrupt controllers — only config+service traffic rides the APB4 slave
FMEDA-verified: SPFM 99.30%, LFM 100.00%, PMHF 1.36×10⁻¹⁰/h — ASIL-B PASS; 37 directed tests plus a formally verified FSM safety invariant

Standards & Compliance

AMBA APB4 (ARM IHI 0024); ISO 26262 ASIL-B SEooC (SPFM 99.30%, LFM 100.00%, PMHF 1.36×10⁻¹⁰/h); IEC 61508 watchdog baseline

Functional Safety

ASIL-B (SEooC) · SPFM 99.30% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
wdt #(
 .ADDR_W(6)
) u_wdt (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the housekeeping layer every SoC needs — timing, watchdogs, reset, and I/O.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Watchdog Timer (WDT)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space