RISC-V Cores & SoC Platform

XiangShan Issue-Queue Payload Parity Overlay

Byte-parity protection for an out-of-order core’s issue-queue / reservation-station payload, checked at the issue edge…

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ASIL-B

target

93.65%

SPFM

84.41%

LFM

PASS

FMEDA

5.6K

gates

0.1.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

XiangShan Issue-Queue Payload Parity Overlay routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Byte-parity protection for an out-of-order core’s issue-queue / reservation-station payload, checked at the issue edge… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

Byte-parity protection for an out-of-order core’s issue-queue (IQ) / reservation-station payload: stored at allocate, re-checked at issue.

Key Features

Per-entry byte parity: one XOR-parity bit per 8-bit lane of the uop payload, stored at allocate (alloc_en) and recomputed and compared at the issue/select edge (issue_en)
Formally proven universal single-bit-upset detection (make formal_xs_iq_parity bmc_fi) plus every odd-per-byte multi-bit upset; same-byte even aliasing is the accepted residual
issue_mismatch feeds safety_monitor’s parity_dp_in for err_code 2, first-event latched until err_clear; a saturating 32-bit n_err event counter adds trend telemetry
Flag, not gate: issue_payload is driven unconditionally — the integrator’s dispatch mux must squash on issue_mismatch, matching the module’s own err_code 2 semantics
No XiangShan RTL vendored: direct allocate/issue ports wire inline beside the real IssueQueue* (backend/issue/IssueQueue.scala) in the integrator’s own checkout, per the xiangshan integration guide
DV/formal-only fault-injection ports (inj_en/inj_idx/inj_chk/inj_mask, gated by IQ_FAULT_INJECT) are absent from production builds; close the loop in make xs_iq_parity (TB 3/3) and SymbiYosys bmc/bmc_fi/cover
Aggregates into xs_safety_island alongside xs_rob_parity/xs_prf_ecc/xs_stq_parity for the xiangshan_safe (ASIL-B) / xiangshan_lockstep (ASIL-D) SKUs

Standards & Compliance

RISC-V OOO issue-queue / reservation-station payload protection; ISO 26262 ASIL-B SEooC (SPFM 93.65%, LFM 84.41%, PMHF 4.43×10⁻⁹/h, pre-sign-off engineering FMEDA)

Functional Safety

ASIL-B (SEooC) · SPFM 93.65% · LFM 84.41% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
xs_iq_parity #(
 .ADDR_W(6)
) u_xs_iq_parity (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in XiangShan Issue-Queue Payload Parity Overlay?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space