XiangShan DCLS Lockstep Comparator (Core-Agnostic Overlay)

What it is

xs_lockstep is a core-agnostic dual-core delay-compare lockstep (DCLS) comparator that adds ASIL-D-class fault detection to a redundant pair of out-of-order RISC-V cores — including a real XiangShan (Nanhu/Kunminghu) generation — without vendoring or modifying a single line of the core’s RTL.

Key Features

• Pure comparator overlay — no core instances, no vendored RTL; parametrized IN_W (checker-input width) / OUT_W (architectural compare width) / DELAY (checker lag, ≥ 1 cycle)
• Binds to any XiangShan generation (or other OOO core pair) via the integrator’s own checkout — XS_RTL=/XiangShan/build/rtl — with zero third-party redistribution to license
• Diverse dual-path comparator (arithmetic inequality + XOR-reduce, cross-checked, KEEP_ATTR) plus a periodic walking-vector self-test sweeping every compared bit — closes the who-checks-the-checker single point (err_code 9)
• KEEP_ATTR-duplicated prime counter (DMR): a stuck-at on the bare prime FSM would otherwise silently blind the live compare; the duplicate divergence is itself a reported fault
• Gate-level fault-injection campaign measures the comparator + prime-FSM region at 100% detected / 0 dangerous — the single biggest lever behind the ASIL-D closure
• lockstep_err (combinational) + recover_req (pulse) on divergence once primed (DELAY+1 cycles from reset); embedded SymbiYosys formal set confirmed vacuity-clean (err_valid/err_code both non-vacuously exercised)
• Composes into xs_safety_island alongside xs_prf_ecc/xs_rob_parity/xs_iq_parity/xs_stq_parity for the full error taxonomy, with an explicit subsumption rule so per-structure single-point DC is never double-counted against the whole-pair DCLS DC

Standards & Compliance

RISC-V (core-agnostic OOO comparator; proven against a real XiangShan Nanhu/Kunminghu binding); ISO 26262 ASIL-D SEooC (informational, pre-sign-off) — standalone SPFM 99.96% / LFM 100.00% / PMHF 5.98×10⁻¹²/h; composed xiangshan_lockstep SKU SPFM 99.96% / LFM 98.62% / PMHF 8.97×10⁻⁹/h

Functional Safety

ASIL-D (SEooC) · SPFM 99.96% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
xs_lockstep #(
  .ADDR_W(6)
) u_xs_lockstep (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.