The deliverable
What you’re licensing
Byte-parity-protected reorder-buffer entry array for an out-of-order CPU. No-vendor XiangShan overlay (19/N-23, Phase 1 block 2). It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:
Synthesizable RTL
Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.
Per-IP FMEDA report
SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.
Safety manual
Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.
IP-XACT + integration docs
A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.
Self-checking testbench
A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.
Byte-parity-protected reorder-buffer entry array for an out-of-order CPU. No-vendor XiangShan overlay (#19/N-23, Phase 1 block 2). ISO 26262 ASIL-B SEooC (informational preview).
Key Features
- Per-entry byte parity: one XOR-parity bit per 8-bit lane of the ROB payload, stored at writeback (wb_en) and recomputed and compared at the in-order commit edge (cm_en) — the safety boundary for an OOO core
- Formally proven universal single-bit-upset detection (make formal_xs_rob_parity bmc_fi) plus every odd-per-byte multi-bit upset; same-byte even aliasing is the accepted, documented residual
- cm_mismatch feeds safety_monitor’s parity_dp_in for err_code 2, first-event latched until err_clear; a saturating 32-bit n_err event counter adds trend telemetry
- 45% FMEDA safe fraction credited to the speculative frontend: a parity fault in a ROB entry squashed pre-commit (mispredict/exception/replay) is re-derived by the refetch and never violates a safety goal (ISO 26262-5 safe fault)
- No XiangShan RTL vendored: the overlay’s writeback/commit ports bind as a parallel shadow store beside the real Rob’s own writeback bus and RobDeqPtrWrapper dequeue pointer, per the xiangshan integration guide
- DV/formal-only fault-injection ports (inj_en/inj_idx/inj_chk/inj_mask, gated by ROB_FAULT_INJECT) are absent from production builds; closed by make xs_rob_parity (TB 5/5) and SymbiYosys bmc/bmc_fi/cover_fi, vacuity-clean
- Aggregates into xs_safety_island alongside xs_prf_ecc/xs_iq_parity/xs_stq_parity for the xiangshan_safe (ASIL-B) / xiangshan_lockstep (ASIL-D) SKUs
Standards & Compliance
RISC-V out-of-order reorder-buffer commit-edge protection; ISO 26262 ASIL-B SEooC (SPFM 92.98%, LFM 84.13%, PMHF 6.3×10⁻⁹/h, pre-sign-off engineering FMEDA)
Functional Safety
ASIL-B (SEooC) · SPFM 92.98% · LFM 84.13% · PASS
ISO 26262:2018 · FMEDA available · Safety Manual included
Register Map
See datasheet for full register reference.
Getting Started
// Minimal instantiation
xs_rob_parity #(
.ADDR_W(6)
) u_xs_rob_parity (
.clk (clk),
.rst_n (rst_n),
// APB4
.p_paddr (paddr),
.p_psel (psel),
.p_penable (penable),
.p_pwrite (pwrite),
.p_pwdata (pwdata),
.p_prdata (prdata),
.p_pready (pready),
// Safety
.err_clear (1'b0),
.err_valid (err_valid),
.err_code (err_code)
);
Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.
Applications
Where it fits
Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.
Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.