AI Inference & Acceleration

KVCE Adaptive-Bit-Width Quantizer

Per-group adaptive INT2/INT4/INT8 KV-cache quantizer for KVCE-Pro — a 2-reduction inline SQNR estimate…

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ASIL-B

target

91.90%

SPFM

87.19%

LFM

PASS

FMEDA

20.0K

gates

0.1.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

KVCE Adaptive-Bit-Width Quantizer routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Per-group adaptive INT2/INT4/INT8 KV-cache quantizer for KVCE-Pro — a 2-reduction inline SQNR estimate… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

Per-group variable-compression allocator for the KVCE (KV-cache compression) family. A component of KVCE-Pro (CTRL[18] ADAPT_EN), catalogued separately for its own golden-model equivalence check and FMEDA.

Key Features

Per-group adaptive bit-width selection among INT2/INT4/INT8, chosen inline from just two streaming reductions (absmax and Σx²) gathered during the existing FILL pass — no per-bit trial quantization, no divide, no logarithm, no per-model calibration
Programmable quality budget via the SQNR\_THRESH register (T, linear Q0 = ⌈10^(target_dB/10)⌉); T=0 reverts the path to fixed-rate, byte-identical to the proven KVCE-Std/Pro quantizer, gated globally by CTRL[18]ADAPT\_EN
2-bit per-group format tag (1=INT2, 2=INT4, 3=INT8) plus a ceil(absmax/qmax) scale ride ahead of the symbols into the self-describing variable-rate packer/unpacker/dequant chain (kvce\_vr\_packer/kvce\_vr\_unpacker/kvce\_vr\_dequant) — bit-exact round trip, the |x−x̂| ≤ scale bound holding per group
Streaming FILL→SELECT→SCALE→EMIT FSM, single lane, GROUP\_MAX-deep buffer (default 128 elements), runtime-programmable group\_size (1..GROUP\_MAX)
Self-contained ASIL-B safety overlay (no integrator Assumption of Use): per-element group-buffer even parity re-checked at read-out → err_code 1, streaming-FSM duplicate-DMR shadow → err_code 9, and an op-count parity strobe → err_code 1, all into one shared safety_monitor
Verified bit-exact against an independent integer golden model over 8 directed cases plus 4000 randomized groups — every chosen width, format tag, scale, and quantized symbol checked, 788,337 checks / 0 failures (make kvce\_adaptive\_quant) — the equivalence check caught and fixed a real absmax² truncation bug that undersized the width on high-dynamic-range groups
FMEDA-verified ASIL-B: SPFM 91.90%, LFM 87.19%, PMHF 3.05×10⁻⁸/h — PASS with more than 15× margin under the 1×10⁻⁷/h target

Standards & Compliance

ISO 26262 ASIL-B SEooC (self-contained diagnostics, no integrator Assumption of Use) — SPFM 91.90%, LFM 87.19%, PMHF 3.05×10⁻⁸/h; deployed inside the KVCE-Pro AXI4 / CHI RN-F KV-cache compression datapath (CTRL[18]ADAPT\_EN)

Functional Safety

ASIL-B (SEooC) · SPFM 91.90% · LFM 87.19% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
kvce_adaptive_quant #(
 .ADDR_W(6)
) u_kvce_adaptive_quant (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in safety-critical edge inference — ADAS, autonomous robotics, and machine vision.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in KVCE Adaptive-Bit-Width Quantizer?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space